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| 型号： | TPS65250RHAR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 4 A SWITCHING REGULATOR, 2200 kHz SWITCHING FREQ-MAX, PQCC40 |
| 封装： | 6 X 6 MM, GREEN, PLASTIC, MO-220VJJD-2, VQFN-40 |
| 文件页数： | 18/38页 |
| 文件大小： | 1782K |
| 代理商： | TPS65250RHAR |
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SLVSAA3B – JUNE 2010 – REVISED JANUARY 2011
The control and power signals used in the design are shown in Table 2.
Table 2. Control and Power Signals
SIGNAL
TYPE
STATUS
FUNCTION
POWER
VIN
I
12-V DC main supply to TPS65250
GND
System ground. All ground pins and power pad should be connected together.
3.3V
O
Output of Buck 1
2.5V
O
Output of Buck 2
7.5V
O
Output of Buck 3
Voltage used to connect the pull-up resistors of the Open Drain outputs
VPULL
O
(PGOOD, GASP).
CONTROL
Enable signals for Buck 1 and Buck 2. Left open they will start automatically
EN1, EN2
I
Active high
once power is applied. If capacitors are fitted to their enable pins, start-up will be
delayed.
Enable signal for Buck 3. Externally enabled by host processor. During the
EN3
I
Active high
release stage (GASP) Buck 3 must stay enabled.
External processor signal to force buck converters in low power mode and
LOW_P
I
Active high
reduce input power.
External 1.14-MHz clock. Device will start with an internal frequency set to
SYNC
I
0.8 MHz.
PGOOD
O
Active low
PGOOD (end of reset signal) to processor. Buck 1 and Buck 3 are monitored.
Release stage of the pump and dump procedure. Input supply collapsed and
GASP
O
Active low
energy stored in CSTG capacitor is released in a controlled way to the input
supply.
The following example illustrates the design procedure for selecting external components for the three buck
converters. The example focuses on BUCK 1, but the procedure can be directly applied to BUCK 2 and 3 as
well. The design goal parameters are given in Table 3.
Table 3. Design Parameters
Output voltage
3.3 V
Transient response 0.5-A to 2-A load step
165 mV
Maximum output current
2 A
Input voltage
12 V nom, 9.6 V to 14.4 V
Output voltage ripple
< 30 mV p-p
Switching frequency
500 kHz
Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, you will want to choose the
highest switching frequency possible since this will produce the smallest solution size. The high switching
frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. However, the highest switching frequency causes extra switching losses, which
hurt the converter’s performance. The converter is capable of running from 300 kHz to 2.2 MHz. Unless a small
solution size is an ultimate goal, a moderate switching frequency of 500 kHz is selected to achieve both a small
solution size and a high efficiency operation. Note however that for xDSL applications is desirable to synchronize
the converter to the system clock running at either 1.1 MHz or 2.2 MHz. If 1.1 MHz is to be used, set the external
resistor to 232 k
for PMIC switching at 800 KHz (~70% of clock frequency).
Output Inductor Selection
To calculate the value of the output inductor, use Equation 14. KIND is a coefficient that represents the amount
of inductor ripple current relative to the maximum output current. In general, KIND is normally from 0.1 to 0.3 for
the majority of applications.
Copyright 2010–2011, Texas Instruments Incorporated
25
Product Folder Link(s): TPS65250
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