参数资料
型号: TPS73601MDBVREP
厂商: Texas Instruments
文件页数: 4/27页
文件大小: 0K
描述: IC REG LDO ADJ .4A SOT23-5
标准包装: 1
稳压器拓扑结构: 正,可调式
输出电压: 1.2 V ~ 5.5 V
输入电压: 1.7 V ~ 5.5 V
电压 - 压降(标准): 0.075V @ 400mA
稳压器数量: 1
电流 - 输出: 400mA(最小值)
电流 - 限制(最小): 400mA
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 标准包装
其它名称: 296-20789-6

TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009 .................................................................................................................................................. www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
V IN range
V EN range
V OUT range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, T J
Storage temperature range
–0.3 to 6
–0.3 to 6
–0.3 to 5.5
Internally limited
Indefinite
–55 to 150
–65 to 150
V
V
V
°C
°C
ESD rating
Human-Body Model - HBM
Charged-Device Model - CDM
2
500
kV
V
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS (1)
BOARD
Low-K (2)
High-K (3)
Low-K (2)
PACKAGE
DBV
DBV
DCQ
R θ JC
64°C/W
64°C/W
15°C/W
R θ JA
255°C/W
180°C/W
53°C/W
DERATING FACTOR
ABOVE T A = 25°C
3.9 mW/°C
5.6 mW/°C
18.9 mW/°C
T A ≤ 25°C
POWER RATING
392 mW
556 mW
1887 mW
T A = 70°C
POWER RATING
216 mW
306 mW
1038 mW
T A = 85°C
POWER RATING
157 mW
222 mW
755 mW
High-K
(3)
DCQ
15°C/W
45°C/W
22.2 mW/°C
2222 mW
1222 mW
889 mW
High-K (3) (4)
DRB
1.2°C/W
40°C/W
25.0 mW/°C
2500 mW
1375 mW
1000 mW
(1)
(2)
(3)
(4)
See the Thermal Protection section for more information related to thermal design.
The JEDEC Low-K (1s) board design used to derive this data was a 3 in × 3 in, two-layer board with 2 oz copper traces on top of the
board.
The JEDEC High-K (2s2p) board design used to derive this data was a 3 in × 3 in, multilayer board with 1 oz internal power and ground
planes, and 2-oz copper traces on the top and bottom of the board.
Based on preliminary thermal simulations.
4
Copyright ? 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP
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