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| 型号： | TPS780330220DRVTG4 |
| 厂商： | Texas Instruments |
| 文件页数： | 19/33页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3.3V/2.2V .15A 6-SON |
| 标准包装： | 250 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3.3V，2.2V |
| 输入电压： | 2.2 V ~ 5.5 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 150mA（最小值） |
| 电流 - 限制（最小）： | 150mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WDFN 裸露焊盘 |
| 供应商设备封装： | 6-SON 裸露焊盘（2x2） |
| 包装： | 带卷 (TR) |
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TI Information — Selective Disclosure
TPS780 Series
savings are calculated for various MSP430 devices
using a TPS780 series with integrated DVS versus a
standard ultralow I Q LDO without DVS. In Table 6 , the
TPS780 series quiescent power is calculated for a V IN
of 4.2V, with the same V IN used for the ultralow I Q
LDO. Quiescent power dissipation in an LDO is the
V IN voltage times the ground current, because zero
load is applied. After the dissipation power is
calculated for the individual LDOs in Table 6 , simple
subtraction outputs the LDO power savings using the
TPS780 series. Table 7 calculates the total system
power savings using a TPS780 series LDO in place
of an ultralow I Q 1.2 μ A LDO in an MSP430F1121
application. There are many different versions of the
MSP430. Actual power savings will vary depending
on the selected device.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1 μ F to 1.0 μ F low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. This capacitor counteracts reactive input
sources and improves transient response, noise
SBVS083D – JANUARY 2007 – REVISED SEPTEMBER 2012
capacitor may be necessary if large, fast rise-time
load transients are anticipated, or if the device is not
located near the power source. If source impedance
is not sufficiently low, a 0.1 μ F input capacitor may be
necessary to ensure stability.
The TPS780 is designed to be stable with standard
ceramic capacitors with values of 1.0 μ F or larger at
the output. X5R- and X7R-type capacitors are best
because they have minimal variation in value and
ESR over temperature. Maximum ESR should be less
than 1.0 ? . With tolerance and dc bias effects, the
minimum capacitance required to ensure stability is
1 μ F.
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance (such as PSRR, output
noise, and transient response), it is recommended
that the printed circuit board (PCB) be designed with
separate ground planes for V IN and V OUT , with each
ground plane connected only at the GND pin of the
device. In addition, the ground connection for the
output capacitor should connect directly to the GND
pin of the device. High ESR capacitors may degrade
PSRR.
rejection,
and
ripple
rejection.
A
higher-value
Table 5. DVS MSP430 Power Savings with the TPS780 Series on selected MSP430 Devices
LPM3 AT V CC = 3V,
LPM3 AT V CC = 3.0V
LPM3 AT V CC =
LPM3 AT V CC = 2.2V
I Q
× I Q
2.2V, I Q
× I Q
μ W SAVINGS
DEVICE
MSP430F1121
MSP430F149
MSP430F2131
MSP430F249
MSP430F413
MSP430F449
( μ A)
1.6
1.6
0.9
1.0
0.9
1.6
( μ W)
4.8
4.8
2.7
3.0
2.7
4.8
( μ A)
0.7
0.9
0.7
0.9
0.7
1.1
( μ W)
1.5
2.0
1.5
2.0
1.5
2.4
USING ONLY DVS
3.3
2.8
1.2
1.0
1.2
2.4
Table 6. Typical Ultralow I Q LDO Quiescent Power Dissipation Versus the TPS780 Series
MSP430 SYSTEM
TYPICAL ULTRALOW I Q
TPS780 SERIES
TPS780 SERIES AT
POWER SAVINGS
TYPICAL ULTRALOW I Q
LDO AT +25°C AMBIENT
LDO AT +25°C AMBIENT
POWER DISSIPATION
TYPICAL I Q AT +25°C
AMBIENT
+25C AMBIENT, POWER
DISSIPATION
USING THE TPS780
SERIES
QUIESCENT POWER
I Q
( μ A)
1.20
I Q × V IN = 4.2V
( μ W)
5.04
TPS780 I Q
( μ A)
0.42
I Q × V IN = 4.2V
( μ W)
1.76
DISSIPATION SAVINGS
( μ W)
3.28
Table 7. Total System Power Dissipation
TOTAL SYSTEM POWER IN
LDO DISSIPATION
MSP430 DISSIPATION
SLEEP MODE 3
Typical 1.2 μ A LDO, no DVS
TPS780 Series with DVS
5.04 μ W
1.76 μ W
4.8 μ W (1)
1.5 μ W (1)
9.84 μ W
3.26 μ W
(1)
Value taken from Table 5 and relative to the MSP430F1121.
Copyright ? 2007–2012, Texas Instruments Incorporated
19
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