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| 型号： | TPS84320RUQT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 3 A SWITCHING REGULATOR, 390 kHz SWITCHING FREQ-MAX, PQCC47 |
| 封装： | 9 X 15 MM, 2.80 MM HEIGHT, GREEN, PLASTIC, QFN-47 |
| 文件页数： | 14/28页 |
| 文件大小： | 903K |
| 代理商： | TPS84320RUQT |
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AGND
RT/CLK
RRT
External Clock
330 kHz to 780 kHz
SLUSAH7
– SEPTEMBER 2011
Synchronization (CLK)
An internal phase locked loop (PLL) has been implemented to allow synchronization between 330 kHz and
780 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a
square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude
must transition lower than 0.8 V and higher than 2.0 V. The start of the switching cycle is synchronized to the
falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be
configured as shown in .
Before the external clock is present, the device works in RT mode and the switching frequency is set by RT
resistor (RRT). When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK
pin is pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to th CLK mode and
the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is
not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to
100 kHz and may shut-down due to internal protection circuits before returning to the switching frequency set by
the RT resistor.
Figure 35. CLK/RT Configuration
The synchronization frequency must be selected based on the output voltages of the devices being
synchronized. Table 7 shows the allowable frequencies for a given range of output voltages. For the most
efficient solution, always synchronize to the lowest allowable frequency. For example, an application requires
synchronizing three TPS84320 devices with output voltages of 1.2 V, 1.8 V and 2.5 V, all powered from
PVIN = 12 V. Table 7 shows that all three output voltages can be synchronized to frquencies between 480 kHz to
630 kHz. For best efficiency, choose 480 kHz as the sychronization frequency.
Table 7. Synchronization Frequency vs Output Voltage
PVIN = 12 V
PVIN = 5 V
SYNCHRONIZATION
RRT (kΩ)
VOUT RANGE (V)
FREQUENCY (kHz)
MIN
MAX
MIN
MAX
330
OPEN
0.8
1.5
380
1000
0.8
1.7
430
499
0.8
2.1
480
324
0.9
2.5
530
237
1.0
2.9
0.8
4.3
580
191
1.1
3.2
630
158
1.2
3.7
680
137
1.3
4.1
730
118
1.4
4.7
780
105
1.5
5.5
Copyright
2011, Texas Instruments Incorporated
21
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