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参数资料
| 型号： | TRF2050PW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20 |
| 封装： | PLASTIC, SO-20 |
| 文件页数： | 25/34页 |
| 文件大小： | 543K |
| 代理商： | TRF2050PW |
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TRF2050
LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER
SLWS030E– JUNE 1996 – REVISED OCTOBER 2000
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
loop enable/disable
The main and auxiliary loops can be enabled and disabled by the contents of the enable bits EM and EA,
respectively. When disabled, all currents in the RF input stages are switched off; the bias currents for the
respective charge-pump circuits are switched off as well. When both loops are disabled (EM = EA = 0), the
reference input stage currents are switched off. The reference chain can be turned off because the serial
interface operates independent of the reference input for the loading of serial words.
Table 8. Loop Enable/Disable
EM
EA
ENABLED
DISABLED
0
Main, Auxiliary, Reference
0
1
Auxiliary, Reference
Main,
1
0
Main, Reference
Auxiliary
1
Main, Auxiliary, Reference
speed-up mode
When the main synthesizer frequency is changed, it may be desirable to increase the loop bandwidth for a short
time in order to achieve a faster lock time. The proportional charge-pump current is increased and the integral
charge-pump current is switched on for the duration of speed-up mode. The section,
charge-pump current
plans, illustrates how the charge-pump currents are a function of the external resistor RN and the programmable
coefficients CN, CL, and CK.
The duration of the speed-up mode is determined by the operational mode of the TRF2050 device: enhanced
performance mode (EPM) or SA7025 emulation mode. In EPM mode, the speed-up mode duration is controlled
as a function of the G field in the B-Word and the reference frequency divider period.
Table 9. Speed-Up Mode
G VALUE
DURATIONEPM
0–14
[(G+1)
× NR × SM × 16]/fREFIN
15
< (NR
× SM)/(fREFIN × 2); which is less than 1/2 a phase detector cycle
When the TRF2050 is operated in SA7025 emulation mode, the speed-up mode duration is a function of the
STROBE signal associated with the A-Word. When the STROBE signal followed by an A-Word write transaction
goes active, the speed-up mode currents begin and persist until the STROBE signal is returned to an inactive
state.
lock detect
The lock condition of the PLL is defined as a phase difference of less than a
±1 cycle on the reference input
REFIN. The LOCK terminal can be polled to determine the synthesizer lock condition of either or both loops.
The lock detect function is described by the Boolean expression:
LOCK
+ LD
Main )
EM
LD
Aux )
EA
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