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参数资料
| 型号： | TRF3750IRGPR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2400 MHz, PQCC20 |
| 封装： | 4 X 4 MM, GREEN, PLASTIC, QFN-20 |
| 文件页数： | 15/37页 |
| 文件大小： | 860K |
| 代理商： | TRF3750IRGPR |
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TRF3750
SLWS146B MARCH 2004 REVISED AUGUST 2007
www.ti.com
22
R Counter Latch
By selecting (0,0) for the control bits DB0 and DB1, the R counter latch is selected. Table 7 shows the setup
of the R counter latch.
Table 7. R Counter Latch
Reserved
Lock
Detect
Precision
Test
Mode Bits
Anti
Backlash
Width
Control
Bits
DB23 DB22 DB21
DB20
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
DLY SYNC
LDP
T2
T1 ABP2 ABP1 R14 R13 R12 R11 R10
R9
R8 R7 R6 R5 R4 R3 R2 R1 C2(0) C1(0)
14-Bit Reference Counter; R
DLY SYNC
R Value
This latch is used primarily to select the R divider for the input reference signal (REFIN). DB2 through DB15
are used to select the chosen value for the 14-bit counter. DB2 is the LSB and DB15 the MSB.
Anti-backlash Pulse
DB16 and DB17 can be used to select the width of the anti-backlash pulse in the PFD. In any PFD
implementation, there is an inherent risk of backlash, a phenomenon that can occur when the device is almost
in lock. In order to ensure that there are always pulses coming out of the charge pump and that therefore the
VCO cannot drift out of lock, the TRF3750 employs an anti-backlash pulse. The user can select the width of
the anti-backlash pulse; the values allowed are 1.5 ns, 3 ns, and 6 ns.
Lock Detect Precision
Setting DB20 of the R counter latch to 0 results in a precision of three cycles for the lock detect, while setting
it to 1 results in a precision of five cycles.
Sync / Delay
DB2122 control the sync/delay operation of the device. If DB21 is 0, then the device is in normal operation.
Assuming DB21 is set to 1, setting DB22 to 0 utilizes a non-delayed form of the RF signal for the
resynchronization of the prescaler output, whereas setting DB22 to 1 utilizes a delayed form.
Reserved Bits
Bits DB18, DB19 and DB23 of the R counter latch are reserved. It is recommended to keep those bits 0 for
normal operation.
N Counter Latch
Setting (DB1, DB0) = (0,1) for the latch control bits selects the N counter latch. Table 8 shows the setup of the
N counter latch.
Table 8. N Counter Latch
Reserved
CP
Gain
Control
Bits l
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
G1 B13 B12 B11 D10
B9
B8
B7
B6
B5
B4
B3
B2 B1 A6 A5 A4 A3 A2 A1 C2(0) C1(0)
X
13-Bit B Counter
6-Bit B Counter
A Counter
The 6 bits DB2DB7 control the value of the A counter. The valid range is from 0 to 63. For example,
programming (DB7, DB6, DB5, DB4, DB3,DB2) = (0,0,0,0,1,0) results in a value of 2 for the A counter.
B Counter
The 13 bits DB8DB20 of the N counter latch control the value of the B counter. The valid range is from 3 to
8191. For example, (DB20, DB19, …, DB10, DB9, DB8) = (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0) results in a value
of 4 for the B counter.
Charge Pump Gain
DB21 of the N counter latch determines when the TRF3750 enters Fastlock Mode. When this bit is 1, the device
switches into fastlock and when this bit is 0, the device exits fastlock (fastlock mode 1).
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