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| 型号： | TRF3750IRGPR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2400 MHz, PQCC20 |
| 封装： | 4 X 4 MM, GREEN, PLASTIC, QFN-20 |
| 文件页数： | 7/37页 |
| 文件大小： | 860K |
| 代理商： | TRF3750IRGPR |
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TRF3750
SLWS146B MARCH 2004 REVISED AUGUST 2007
www.ti.com
15
FUNCTIONAL DESCRIPTION
REFIN Stage
This input typically comes from an external oscillator and is the reference used to synthesize the desired
frequency on the output of the complete PLL. The equivalent schematic of this section is given in Figure 24.
The output of this section goes to the R divider, so that the desired PFD frequency can be implemented.
R
PD
PDZ
PD
PDZ
Figure 24. REFIN Stage
RFIN Stage
Figure 25 shows the input stage of the TRF3750. This is where the output of the external VCO is fed back to the
synthesizer. The RFIN signal subsequently feeds the prescaler section.
VBIAS
AVDD
RFIN
RFINB
Figure 25. RFIN Stage
Prescaler Stage
This stage divides down the RFIN frequency before the A and B counters. This is a dual-modulus prescaler and the
user can select any of the following settings: 8/9, 16/17, 32/33, and 64/65.
A and B Counter Stage
The TRF3750 includes a 6-bit A counter and a 13-bit B counter that operate on the output of the prescaler. The A
counter can take values from 0 to 63, while the B counter can take values from 3 to 8191. Also, the value for the B
counter has to be greater than or equal to the value for the A counter. These are CMOS devices, and can easily
operate up to 200 MHz. The selection of the prescaler needs to be such that the resultant frequency does not exceed
the rated 200-MHz threshold.
R Divider
The output of the REFIN stage is fed into the R divider stage. The 14-bit R divider allows the input reference frequency
to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to
16,383 are allowed.
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