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参数资料
| 型号： | TRF3761-BIRHAR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40 |
| 封装： | GREEN, PLASTIC, MO-220VJJD-2, QFN-40 |
| 文件页数： | 36/60页 |
| 文件大小： | 1736K |
| 代理商： | TRF3761-BIRHAR |
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(
)
OUT
PFD
COUNTER
F
N =
=
A
+ Prescalar
× B
num
F
(4)
integer
decimal
num
COUNTER
integer
COUNTER
num
decimal
N
= x
y
,
Prescalar
B
= x
and A
= Prescalar
× y
(5)
Reference Divider
REF_IN
DIV
PFD
F
R
=
F
(6)
(
)
REF_IN
OUT
DIV
PFD
COUNTER
num
COUNTER
F
= F
× N =
× A
+ Prescalar
× B
R
(7)
Phase Frequency Detector (PFD) and Charge Pump Stage
Mux Out
Div 1/2/4
Serial interface
CHIP ENABLE
Buffer Power Down
External VCO IN
www.ti.com ............................................................................................................................................... SLWS181J – OCTOBER 2005 – REVISED AUGUST 2008
TRF3761 includes a 14-bit RDiv, also known as RDiv, that allows the input reference frequency to be divided
down to produce the reference clock to the phase frequency detector (PFD) this clock is also known as FPFD
which is also the channel step size. Division ratios from 1 to 16,383 are allowed. To determine RDiv use
The output frequency (Fout) is determined using Equation 7.
The outputs of the RDiv and the N counter are fed into the PFD stage, where the two signals are compared in
frequency and phase. The TRF3761 features an anti-backlash pulse, whose width is controllable by the user
through the serial programming interface. The PFD feeds the charge pump, whose output current pulses are fed
into an external loop filter, which eventually produces the tuning voltage needed to control the integrated VCO to
the desired frequency.
MUX_OUT pin (39) provides a communication port to the microcontroller circuit. See Table 4 in the Application
Information section.
Div 1/2/4 is the frequency divider for the TRF3761. This circuit can be programmed thru the serial programming
interface (SPI) to divide the output frequency of the VCO by 1, 2 or 4. This feature allows for the same loop filter
design to be used for any of the 3 divide by modes, 1, 2 and 4. For example, if the VCO is running at 1499MHz
to 1608MHz band then with the same exact circuit, run the output in the divide by 2 mode 749.5MHz to 804MHz
band or in the divide by 4 mode 374.75MHz to 402MHz.
The programming interface pins (3, 4, 5) to the chip are the serial programming interface (SPI). The interface
requires a Clock, Data, and Strobe signal to operate. See timing diagram Figure 83.
This feature provides a way to shut down the chip when not needed in order to conserve power. CHIP_EN Pin
(2) needs to be High for normal operation.
PD_OUTBUFF pin (1), when enabled in software can provide a -40dB reduction in the output power while the
VCO is locked and running. This feature is to help with isolation between RX and TX.
EXT_VCO_IN pin (18) allows for the use of an external VCO to use the phase lock loop circuit in the TRF3761.
This feature enables higher frequencies to be synthesized.
Copyright 2005–2008, Texas Instruments Incorporated
41
Product Folder Link(s): TRF3761
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相关代理商/技术参数 |
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| TRF3761-BIRHARG4 | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3761-BIRHAT | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3761-BIRHATG4 | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3761-C | 制造商:TI 制造商全称:Texas Instruments 功能描述:INTEGER-N PLL WITH INTEGRATED VCO |
| TRF3761-CIRHAR | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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