参数资料
型号: TRF3761-BIRHAR
厂商: TEXAS INSTRUMENTS INC
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
封装: GREEN, PLASTIC, MO-220VJJD-2, QFN-40
文件页数: 45/60页
文件大小: 1736K
代理商: TRF3761-BIRHAR
THERMAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
www.ti.com ............................................................................................................................................... SLWS181J – OCTOBER 2005 – REVISED AUGUST 2008
TERMINAL FUNCTIONS (continued)
TERMINAL(1)
I/O
DESCRIPTION
NAME
NO.
External bias resistor for setting the internal reference current requires a 4.75K
RBIAS2
19
I/O
ohm resister to ground.
Analog power supply, requires 4.5 to 5.25 V, Suggested decoupling, 0.1uF and
AVDD
21
10
F capacitors in parallel.
Power supply for VCO core and buffer, requires 4.5 to 5.25 V, Suggested
AVDD_CAPARRAY
23
decoupling, 0.1
F and 10pF capacitors in parallel.
Power supply for VCO core and buffer, requires 4.5 to 5.25 V, Suggested
AVDD_BUF
24
decoupling, 0.1
F and 10pF capacitors in parallel.
Power supply for VCO core and buffer, requires 4.5 to 5.25 V, Suggested
AVDD_VCO
25
decoupling, 0.1uF and 10pF capacitors in parallel.
VCTRL_IN
26
I
VCO control voltage, the output of the loop filter is applied to this pin.
External bias resistor for setting charge pump reference current, requires 2.37K
RBIAS1
28
I/O
ohm resistor to ground.
Power supply for band gap current bias, requires 4.5 to 5.25 V, Suggested
AVDD_BIAS
29
decoupling, 0.1
F and 10pF capacitors in parallel.
10, 11, 12, 16, 20, 22,
GND
Analog ground
27, 30, 31, 33, 37
Power supply for FUSE cell, requires 4.5 to 5.25V. Suggested decoupling, 0.1
F,
AVDD
32
1nF and 1pF capacitors in parallel.
CPOUT
34
O
Charge pump output, connected to the input of loop filter.
Analog power supply for charge pump, requires 4.5 to 5.25 V, Suggested
AVDD_CP
35
decoupling, 0.1
F and 10pF capacitors in parallel
Power supply for REF_IN circuitry, requires 4.5 to 5.25 V, Suggested decoupling,
AVDD_REF
36
0.1
F and 10pF capacitors in parallel.
REF_IN
38
I
Reference signal input, reference oscillator input of 10MHz to 104MHz.
Generally used for digital lock detect, can be used to verify locked condition by
MUX_OUT
39
O
microcontroller, high = locked, low = unlocked.
Power supply for the digital regulator, requires 4.5 to 5.25 V, Suggested
DVDD2
40
decoupling, 0.1
F and 10pF capacitors in parallel.
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Soldered slug, no airflow
26
°C/W
θ
JA
Thermal derating, junction-to-ambient
Soldered slug, 200-LFM airflow
20.1
°C/W
Soldered slug, 400-LFM airflow
17.4
°C/W
(1)
Determined using JEDEC standard JESD-51 with High K board
Over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
Supply voltage range(2)
–0.3 to 5.5
V
Digital I/O voltage range
–0.3 to VCC +0.3
V
TJ
Operating virtual junction temperature range
–40 to 150
°C
Tstg
Storage temperature range
–65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2)
All voltage values are with respect to network ground terminal.
Copyright 2005–2008, Texas Instruments Incorporated
5
Product Folder Link(s): TRF3761
相关PDF资料
PDF描述
TRF3761-KIRHAT PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
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