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参数资料
| 型号： | TRF3761-BIRHAT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40 |
| 封装： | GREEN, PLASTIC, MO-220VJJD-2, QFN-40 |
| 文件页数： | 37/60页 |
| 文件大小： | 1736K |
| 代理商： | TRF3761-BIRHAT |
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APPLICATION INFORMATION
Initial Calibration and Frequency Setup at Power Up
SLWS181J – OCTOBER 2005 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com
The integrated high performance VCO requires an internal frequency calibration at power up. To perform such
calibration the following procedure is recommended:
Apply 5V power supply to IC.
Apply an input reference frequency to pin (38) and ensure the signal is stable.
Turn on the TRF3761 using the chip enable pin (CHIP_EN, pin 2), by applying 5V.
Register 1
Setup the device through Register 1 referencing Table 1.
a. The first 4 bits of the 32-bit code sent to the chip are set DB <3:0> to 0000; which is the address of
register 1.
b. Bit 5, DB4, sets the soft reset for the chip. Soft reset allows for the registers to be reset without powering
down the chip. If a soft reset is used then write to register 1 twice: once with DB4 set high and once with
DB4 set low. Typically, this bit is only used when the chip has been powered up and registers 1, 2, and 3
have already been written to, so on power-up reset is not required, so DB4 is, by default, set low.
c. DB <7: 5> sets the charge pump current based on the resistor value on pin 28 of the TRF3761 and the
decimal value of Register 1, DB<7:5> used in Equation 1. This equation reduces to Equation 2, where
N = decimal value of [Reg1 DB<7:5>].
d. DB <9: 8> sets the mode of the chip. The mode is how the device will or will not divide down the VCO’s
frequency. There are 3 choices for the mode setting, divide by 1, 2 or 4 per Table 1. For example, if
393.75MHz is required from the TRF3761 which has a main frequency of 1575MHz then the divide-by-4
mode is chosen by setting DB <9: 8> to 10.
e. DB <11:10> controls the output buffer. Both of these are set to 00 by default, so the buffer is controlled
internally. See Table 1 for more information.
f.
DB <25:12> sets the RDiv value. Once the calculations under the Synthesizing a Selected Frequency
section have been completed the value is known, based on the external reference oscillator. The value
for R is entered into the DB <25:12>. For example, if the reference oscillator is at a frequency (FREF_IN) of
61.44MHz and a channel step size of 120kHz is required, which is also the frequency (FPFD) the phase
frequency detector will use to compare against the VCO's output frequency (FOUT), then FREF_IN /FPFD =
512, which is entered as follows: MSB: LSB 0001000000000.
g. By default, DB <27:26> are set to 00 for a 1.5ns delay on the anti-backlash pulse width. See Table 1 for
more information.
h. DB 28 is set to 1 for positive by default. See Table 1 for more information.
i.
DB 29 is set to 0 for normal operation. See Table 1 for more information.
j.
DB 30 is set to 0 by default. See Table 1 for more information.
k. DB 31 is set to 0 by default. See Table 1 for more information.
Register 2
Initiate calibration procedure by programming register 2 as follows: Reference Table 2
a. The first 4 bits of the 32-bit code sent to the chip are set DB <3:0> to 0001; which is the address of
register 2.
b. Use bits DB<17, 4> of register 2 to specify the input reference frequency in MHz. The value is split into
an integer and a fraction part. For example: to insert a fREF of 30.72MHz, set:
–
DB<10, 4> (integer part) equal to 0011110 (30) and
–
DB<17, 11> (fraction part) equal to 1001000 (72).
42
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TRF3761
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相关代理商/技术参数 |
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|---|---|
| TRF3761-BIRHATG4 | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3761-C | 制造商:TI 制造商全称:Texas Instruments 功能描述:INTEGER-N PLL WITH INTEGRATED VCO |
| TRF3761-CIRHAR | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3761-CIRHARG4 | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| TRF3761-CIRHAT | 功能描述:时钟合成器/抖动清除器 Low Noise Integer N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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