参数资料
型号: TRF3761-BIRHAT
厂商: TEXAS INSTRUMENTS INC
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 104 MHz, PQCC40
封装: GREEN, PLASTIC, MO-220VJJD-2, QFN-40
文件页数: 38/60页
文件大小: 1736K
代理商: TRF3761-BIRHAT
Re-Calibration After Power Up
www.ti.com ............................................................................................................................................... SLWS181J – OCTOBER 2005 – REVISED AUGUST 2008
c. Set DB<30:18> of register 2 to the desired frequency. For example: 2200MHz would be 0100010011000
(2200).
d. Set DB31of register 2 to 1 to start the calibration. The VCO calibration runs for 5ms. During the cal
procedure it will not be possible to program register 2 and 3. At the end of the calibration, bit DB31 of
register 2 resets to 0.
e. Subsequent frequency programming requires DB31 to be set to 0.
Register 3
Completion of the frequency set up, on initial calibration, cannot proceed until 5ms has elapsed, due to full
calibration, then it will require that the A and B values, the prescalar ratio, be known. See Synthesizing a
Selected Frequency section below for calculation. Reference Table 3.
a. The first 4 bits of the 32-bit code sent to the chip are set DB <3:0> to 0010; which is the address of
register 3.
b. DB<5:4> sets the prescalar ratio, 8/9, 16/17, 32/33, 64/65. For example: if 16/17 are required, set the
register bits DB<5:4> to 01.
c. DB<11:6> sets the A value for the N counter. For example: if A is 4, set DB<11:6> as follows: 000100 (4).
d. DB<24:12> sets the B value for the N counter. For example: if B is 1156, set DB<24:12> as follows:
0010010000100 (4).
e. DB<28:25> sets the TEST_MUX. This allows the user to check via the microcontroller the state of the
TRF3761 by programming it to one of 6 states. The most common state to use is the Digital lock Detect
which places the pin in a logic high state with indicates the VCO is locked.
Table 4. MUX-Out Settings
STATE
DB<28:25>
STATE
DB<28:25>
3-state o/p ( High impedance state on Pin 39)
0000
RDiv o/p (Shows R-value on Pin 39)
0100
Digital lock Detect (High when locked on Pin 39)
0001
Analog lock detect (High when locked on Pin 39)
0101
N-Divider o/p (Shows N-value on Pin 39)
0010
Read back ( read back register settings)
0110
DVDD (internal TI use)
0011
DGND (internal TI use)
0111
f.
DB29 sets the START LOCK, which is set to 0, on the initial frequency setup and then set to 1 on
additional frequency changes.
Once all registers are written, the TRF3761 will lock to the desired frequency. In order to change the frequency
once the initial calibration is complete, only registers 2 and 3 need to be reprogrammed. No calibration is
required.
Assuming the TRF3761 is powered up and operational, a VCO calibration is also possible without powering
down the IC. To perform such calibration the following procedure is recommended:
Set bit DB4 (RESET) of register 1 to 1. This performs a software reset and clears all registers of VCO
calibration data. Once the reset command is issued then DB4 of register 1 will need to be set to 0.
Repeat the Initial Calibration and Frequency setup at Power up section, skipping the power up section and
performing the register programming sequence.
Copyright 2005–2008, Texas Instruments Incorporated
43
Product Folder Link(s): TRF3761
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