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| 型号： | TS83C51RD2ZZZ-VIA |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 33/72页 |
| 文件大小： | 698K |
| 代理商： | TS83C51RD2ZZZ-VIA |
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Rev. B - Aug. 24, 1999
39
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
Table 20. Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 21. IE Register
IE - Interrupt Enable Register (A8h)
Reset Value = 0000 0000b
Bit addressable
IPH.x
IP.x
Interrupt Level Priority
0
0 (Lowest)
0
1
0
2
1
3 (Highest)
7
6
5
4
3
2
1
0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic
Description
7
EA
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt
enable bit.
6
EC
PCA interrupt enable bit
Clear to disable . Set to enable.
5
ET2
Timer 2 overow interrupt Enable bit
Clear to disable timer 2 overow interrupt.
Set to enable timer 2 overow interrupt.
4
ES
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
3
ET1
Timer 1 overow interrupt Enable bit
Clear to disable timer 1 overow interrupt.
Set to enable timer 1 overow interrupt.
2
EX1
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
1
ET0
Timer 0 overow interrupt Enable bit
Clear to disable timer 0 overow interrupt.
Set to enable timer 0 overow interrupt.
0
EX0
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TS83C51RD2ZZZ-VIAD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
| TS83C51RD2ZZZ-VIBB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
| TS83C51RD2ZZZ-VIBD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
| TS83C51RD2ZZZ-VIBR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
| TS83C51RD2ZZZ-VIEB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
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