参数资料
型号: TSA5059ATS/C1,118
厂商: NXP SEMICONDUCTORS
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 2700 MHz, PDSO16
封装: PLASTIC, SSOP-16
文件页数: 12/24页
文件大小: 118K
代理商: TSA5059ATS/C1,118
2000 Oct 24
2
Philips Semiconductors
Product specication
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059A
FEATURES
Complete 2.7 GHz single chip system
Optimized for low phase noise
Selectable divide-by-two prescaler
Operation up to 2.3 GHz without divide-by-two prescaler
(satellite zero-IF applications) and up to 2.7 GHz with
divide-by-two prescaler
Selectable reference divider ratio
Selectable crystal or comparison frequency output
Four selectable charge pump currents
Four selectable I2C-bus addresses
Standard and fast mode I2C-bus
I2C-bus compatible with 3.3 and 5 V microcontrollers
5-level Analog-to-Digital Converter (ADC)
Low power consumption
Three I/O ports and one output port.
APPLICATIONS
Satellite zero-IF and non-zero-IF tuning systems
Digital set-top boxes.
GENERAL DESCRIPTION
The TSA5059A is a single chip PLL frequency synthesizer
designed for satellite tuning systems up to 2.7 GHz.
The RF preamplifier drives the 17-bit main divider enabling
a step size equal to the comparison frequency, for an input
frequency up to 2.3 GHz covering the complete satellite
zero-IF frequency range. A fixed divide-by-two additional
prescaler can be inserted between the preamplifier and
the main divider for a frequency between 2.3 and 2.7 GHz.
In this case, the step size is twice the comparison
frequency.
The comparison frequency is obtained from an on-chip
crystal oscillator that can also be driven from an external
source. Either the crystal frequency or the comparison
frequency can be switched to the XT/COMP output pin to
drive the reference input of another synthesizer or the
clock input of a digital demodulation IC.
Both divided and comparison frequency are compared into
the fast phase detector which drives the charge pump.
The loop amplifier is also on-chip, excepted an external
NPN transistor to drive directly the 33 V tuning voltage.
Control data is entered via the I2C-bus; five serial bytes are
required to address the device, select the main divider
ratio, the reference divider ratio, program the four output
ports, set the charge pump current, select the prescaler by
two, select the signal to switch to the XT/COMP output pin
and select a specific test mode. Three of the four output
ports can also be used as input ports and a 5-level ADC is
provided. Digital information concerning the input ports
and the ADC can be read out of the TSA5059A on the SDA
line (one status byte) during a READ operation. A flag is
set when the loop is ‘in-lock’ and is read during a READ
operation, as well as the Power-on reset flag. The device
has four programmable addresses, programmed by
applying a specific voltage at pin AS, enabling the use of
multiple synthesizers in the same system.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TSA5059AT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
TSA5059ATS
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
相关PDF资料
PDF描述
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相关代理商/技术参数
参数描述
TSA5059T 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.7 GHz I2C-bus controlled low phase noise frequency synthesizer
TSA5059TS 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.7 GHz I2C-bus controlled low phase noise frequency synthesizer
TSA5060A 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.3 GHz I2C-bus controlled low phase noise frequency synthesizer
TSA5060AT 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.3 GHz I2C-bus controlled low phase noise frequency synthesizer
TSA5060AT/C1,518 功能描述:IC SYNTH FREQ 1.3GHZ 16-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器,零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP(0.173",4.40mm 宽) 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG