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参数资料
| 型号： | TSA5059ATS/C1,118 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2700 MHz, PDSO16 |
| 封装： | PLASTIC, SSOP-16 |
| 文件页数： | 2/24页 |
| 文件大小： | 118K |
| 代理商： | TSA5059ATS/C1,118 |
2000 Oct 24
10
Philips Semiconductors
Product specication
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059A
XT/COMP frequency output
It is possible to output either the crystal or the comparison
frequency at pin XT/COMP to be used in the application.
For example, to drive a second PLL synthesizer saving a
quartz crystal. To output fxtal it is necessary to set bit XCE
to logic 1 and bit XCS to logic 0 or bit XCE to logic 0 and
bit XCS to logic 1 during a test mode, while to output fcomp
it is necessary to set both bits XCE and XCS to logic 1.
If the output signal at this pin is not used it is recommended
to disable it by setting both bits XCE and XCS to logic 0.
Table 10 shows how this pin is programmed. At power-on
the XT/COMP output is set with the fxtal signal selected.
Prescaler enable
The TSA5059A is able to work with the relation
fcomp = step size for an input frequency up to 2.3 GHz,
covering the complete satellite zero-IF frequency range.
For applications with an input frequency higher than
2.3 GHz it is necessary to use the prescaler by 2.
The prescaler is selected by setting bit PE to logic 1 and
it is not in use if bit PE is set to logic 0.
For satellite zero-IF applications (frequency between
950 and 2150 MHz), and especially if it is important to
reach a low phase noise on the controlled VCO, it is
recommended to set bit PE to logic 0 and not to use the
prescaler allowing the comparison frequency to be equal
to the step size.
Test modes
It is possible to access the test modes by setting bit XCE
to logic 0 and bit XCS to logic 1. One specific test mode is
then selected using bits T2, T1 and T0 as described in
Table 10.
Table 10 XT/COMP and test mode selection; note 1
Notes
1. X = don’t care.
2. Status at Power-on reset.
XCE
XCS
T2
T1
T0
XT/COMP OUTPUT
TEST MODE
0
X
disabled
normal operation
1
0
XXX
fxtal
normal operation
1
XXX
fcomp
normal operation
01000
fxtal
test operation: charge pump sink;
status byte bit FL = 1
01001
fxtal
test operation: charge pump source;
status byte bit FL = 0
01010
fxtal
test operation: charge pump disabled;
status byte bit FL = 0
01011
fxtal
test operation: 1
2fDIV switched to Port P0
011
X
fxtal
test operation: drive output (pin DRIVE)
is off (low-voltage) to allow the tuning
voltage to reach the maximum value;
note 2
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSA5059T | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5059TS | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5060A | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.3 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5060AT | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.3 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5060AT/C1,518 | 功能描述:IC SYNTH FREQ 1.3GHZ 16-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
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