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| 型号： | TSA5060AT/C1,518 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16 |
| 封装： | 3.90 MM, PLASTIC, MS-012, SOT-109-1, SOP-16 |
| 文件页数： | 21/24页 |
| 文件大小： | 119K |
| 代理商： | TSA5060AT/C1,518 |
2000 Oct 24
6
Philips Semiconductors
Product specication
1.3 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5060A
The TSA5060A is controlled via the two-wire I2C-bus.
For programming, there is one 7-bit module address and
bit R/W for selecting READ or WRITE mode.
To be able to have more than one synthesizer in an
I2C-bus system, one of four possible addresses is selected
depending on the voltage applied at pin AS (see Table 3).
The TSA5060A fulfils the fast mode I2C-bus, according to
the Philips I2C-bus specification. The I2C-bus interface is
designed in such a way that pins SCL and SDA can be
connected either to 5 or 3.3 V pulled-up I2C-bus lines,
allowing the PLL synthesizer to be connected directly to
the bus lines of a 3.3 V microcontroller.
WRITE mode: R/W=0
After the address transmission (first byte), data bytes can
be sent to the device (see Table 1). Four data bytes are
needed to fully program the TSA5060A. The bus
transceiver has an auto-increment facility that permits
programming of the TSA5060A within one single
transmission (address + 4 data bytes).
The TSA5060A can also be partly programmed on the
condition that the first data byte following the address is
byte 2 or 4. The meaning of the bits in the data bytes is
given in Table 1. The first bit of the first data byte indicates
whether byte 2 (first bit is logic 0) or byte 4 (first bit is
logic 1) will follow. Until an I2C-bus STOP condition is sent
by the controller, additional data bytes can be entered
without the need to re-address the device.
To allow a smooth frequency sweep for fine tuning, and
while the data of the dividing ratio of the main divider is in
data bytes 2, 3 and 4, it is necessary to change the
frequency to send the data bytes 2 to 5 in a repeated
sending, or to finish an incomplete transmission by a
STOP condition. Repeated sending of data bytes 2 and 3
without ending the transmission does not change the
dividing ratio. To illustrate, the following data sequences
will change the dividing ratio:
Bytes 2, 3, 4 and 5
Bytes 4, 5, 2 and 3
Bytes 2, 3, 4 and STOP
Bytes 4, 5, 2 and STOP
Bytes 2, 3 and STOP
Bytes 2 and STOP
Bytes 4 and STOP.
Table 1
Write data format
Note
1. MSB is transmitted first.
BYTE
DESCRIPTION
MSB(1)
LSB
CONTROL BIT
1
address
1
0
MA1
MA0
0
A
2
programmable divider
0
N14
N13
N12
N11
N10
N9
N8
A
3
programmable divider
N7
N6
N5
N4
N3
N2
N1
N0
A
4
control data
1
N16
N15
PE
R3
R2
R1
R0
A
5
control data
C1
C0
XCE
XCS
P3
P2/T2
P1/T1
P0/T0
A
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSA5060ATS | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.3 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5060ATS/C1,118 | 功能描述:IC SYNTH FREQ 1.3GHZ 16-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| TSA5060ATS/C2,118 | 制造商:NXP Semiconductors 功能描述: |
| TSA-5090 | 制造商:Quest Technology International Inc 功能描述: |
| TSA-5091 | 制造商:Quest Technology International Inc 功能描述: |
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