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| 型号： | TSB14C01MHV |
| 英文描述： | IC APEX 20KE FPGA 160K 484-FBGA |
| 中文描述： | 收发器 |
| 文件页数： | 30/35页 |
| 文件大小： | 224K |
| 代理商： | TSB14C01MHV |
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6
–
10
detect the subaction gap before the bus is asserted by another node (upon detecting a subaction gap). The
duration of the subaction gap ensures that another node asserting the bus after an acknowledge gap has
been detected by this time.
Arbitration Reset Gap
—
Appears before asynchronous transfers when the fairness interval starts. A node
should detect the occurrence of an arbitration reset gap after the bus has been in an unasserted state for
at least 28 arbitration clock times (approximately 569.66 ns), but should not assert the bus until a total of
32 arbitration clock times (approximately 651.04 ns) have occurred. This requirement ensures that a node
is given adequate time to detect the arbitration reset gap before the bus is asserted by another node (upon
detecting an arbitration reset gap). The duration of the arbitration reset gap ensures that another node
asserting the bus after a subaction gap or an acknowledge gap has been detected by this time.
If a node is waiting for the occurrence of a particular gap and the bus has become idle for the specified time
(e.g., 32 arbitration clock times for an arbitration reset gap), the node detects the gap and asserts the bus.
An asserted signal propagates through the node decision/transceiver circuitry and onto the bus soon
enough to allow arbitration to occur properly.
6.3
Arbitration Sequence
The TSB14AA1A uses a particular arbitration sequence to arbitrate the bus between competing modules. The
sequence used consists of a 4-bit priority field and a 6-bit arbitration number field.
6.3.1
Priority
Within the arbitration sequence, the arbitration number is preceded by four bits that define a priority level. The method
by which priority is assigned is to be determined by the system integrator with two exceptions. The lowest priority (all
zeros) is reserved for fair arbitration and the highest priority (all ones) is reserved for cycle start requests. This allows
14 priority levels to be used for the urgent arbitration process.
The use of an urgent priority class allows nodes to be granted a large portion of the bandwidth on the bus. High priority
nodes are granted the bus before lower priority nodes during urgent allocation of the bus, allowing such nodes to be
granted more bandwidth.
In order to ensure forward progress, the lowest priority level is reserved for fair arbitration. This allows all nodes
arbitrating with this priority level to be allowed one fair access to the bus for each fairness interval. For fair arbitration,
the value of the arbitration number has a minimal impact on the allocation of the bus. Although nodes with higher
arbitration numbers are granted the bus sooner, there is only a small decrease in latency.
6.3.2
Arbitration Number
The arbitration sequence uses a unique arbitration number for each module. This 6-bit number is the same as the
node Physical_ID. When less than 6-bits are provided for the arbitration number, they occupy the MSBs of the
arbitration number. The remaining bits are zero-filled. The MSBs are transmitted first.
NOTE:
If the serial bus is contained within a host backplane, it is expected that the arbitration
number (i.e., Physical_ID) is set by the host backplane at power up (e.g., with a built-in slot
identifier or configuration mechanism).
This number is software programmable to facilitate testing and to allow for consistent system operation and
repeatability.
相关PDF资料 |
PDF描述 |
|---|---|
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
| TSB21LV03CHV | IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB2203X6MMX30M | IC APEX 20KE FPGA 200K 240-PQFP |
| TSB2204.5X12MMX20M | IC APEX 20KE FPGA 200K 240-PQFP |
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