参数资料
型号: TSC21020F-20SBSC
英文描述: IC CYCLONE III FPGA 40K 484UBGA
中文描述: 数字信号处理器| 32位|的CMOS | RAD数据通信硬| QFL | 256PIN |陶瓷
文件页数: 40/51页
文件大小: 763K
代理商: TSC21020F-20SBSC
40
TSC21020F
4153F
AERO
06/03
Figure 13.
Output Enable/Disable
Test Conditions
Output Disable Time
Output pins are considered to be disable when they stop driving, go into a high-imped-
ance state, and start to decay from their output high or low voltage. The time for the
voltage on the bus to decay by
V is dependent on the capacitive load, C
L
, and the load
current, I
L
. It can be approximated by the following equation:
The output disable time (t
DIS
) is the difference between t
MEASURED
and t
DECAY
as shown
in Figure 13. The time t
MEASURED
is the interval from when the reference signal switches
to when the output voltage decays
V from the measured output high or output low volt-
age. t
DECAY
is calculated with
V equal to 0.5V, and test loads C
L
and I
L
.
Output Enable Time
Output pins are considered to be enabled when they have made a transition from a
high-impedance state to when they start driving. The output enable time (t
ENA
) is the
interval from when a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown in the Output Enable
/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement
value is that of the first pin to start driving.
t
DECAY
C
V
I
L
--------------
=
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