参数资料
型号: TSC21020F-20SBSC
英文描述: IC CYCLONE III FPGA 40K 484UBGA
中文描述: 数字信号处理器| 32位|的CMOS | RAD数据通信硬| QFL | 256PIN |陶瓷
文件页数: 41/51页
文件大小: 763K
代理商: TSC21020F-20SBSC
41
TSC21020F
4153F
AERO
06/03
Figure 14.
Equivalent Device Loading for AC Measurements (Includes all Fixtures)
Example System Hold
Time Calculation
To determine the data output hold time in a particular system, first calculate t
DECAY
using
the above equation. Choose
V to be the difference between the TSC21020F
s output
voltage and the input threshold for the device requiring the hold time. A typical
V will be
0.4V. C
L
is the total bus capacitance (per data line), and I
L
is the total leakage or three-
state current (per data line). The hold time will be t
DECAY
plus the minimum disable time
(i.e. t
HDWD
for the write cycle).
Figure 15.
Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
Capacitive Loading
Output delays are based on standard capacitive loads: 100 pF on address, select, page
and strobe pins, and 50 pF on all others (see Figure 14). For different loads, these tim-
ing parameters should be derated. See the Hardware Configuration chapter of the
ADSP-21020 User
s Manual from Analog Devices for further information on derating of
timing specifications.
Figures 16 and 17 show how the output rise time varies with capacitance. Figures 18
and 19 show how output delays vary with capacitance. Note that the graphs may not be
linear outside the ranges shown.
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相关代理商/技术参数
参数描述
TSC21020F-20SBSL1 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC
TSC21020F-20SBSL2 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC
TSC21020F-20SBSL3 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC
TSC2102BIDA 制造商:Rochester Electronics LLC 功能描述:- Bulk
TSC2102BIDAR 制造商:Rochester Electronics LLC 功能描述:- Bulk