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| 型号： | TSC8051C1XXX-12CGD |
| 元件分类： | 8位微控制器 |
| 英文描述： | 8-Bit Microcontroller for Digital Computer Monitors |
| 中文描述： | 8位数字的电脑显示器微控制器 |
| 文件页数： | 6/31页 |
| 文件大小： | 321K |
| 代理商： | TSC8051C1XXX-12CGD |
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TSC8051C1
Rev. D (14 Jan. 97)
14
MATRA MHS
7. Peripherals Functional Description
For detailed functionnal description of standard 80C51
peripherals, please refer to C51 Family, Hardware
Description and Programmer’s Guides.
7.1. Watchdog Timer
The watchdog timer consists of a 4–bit timer with a
17–bit prescaler as shown in Figure 9. The prescaler is
fed with a signal whose frequency is 1/12 the oscillator
frequency (1MHz with a 12MHz oscillator).
The 4–bit timer is decremented every ‘t’ seconds, where:
t = 12 x 131072 x 1/fosc. (131.072ms at fosc = 12MHz).
Thus, the interval may vary from 131.072ms to
2097.152ms in 16 possible steps (see Table 3. ).
The watchdog timer has to be reloaded (write to HWDR
SFR) within periods that are shorter than the
programmed
watchdog
interval,
otherwise
the
watchdog timer will underflow and a system reset will
be generated which will reset the TSC8051C1.
HWDR: Hardware WatchDog Register
MSB
SFR E6h
LSB
WTE
–
WT3
WT2
WT1
WT0
Symbol
Position
Name and Function
WT0
HWDR.0
Watchdog Timer Interval bit 0.
WT1
HWDR.1
Watchdog Timer Interval bit 1.
WT2
HWDR.2
Watchdog Timer Interval bit 2.
WT3
HWDR.3
Watchdog Timer Interval bit 3.
–
HWDR.4
Reserved for test purpose, must remain to 0 for normal operation.
–
HWDR.5
(Reserved).
–
HWDR.6
(Reserved).
WTE
HWDR.7
Watchdog Timer Enable bit. Setting this bit activates watchdog operation.
Table 3. Watchdog timer interval value format.
WT3
WT2
WT1
WT0
Interval
0
t x 16
0
1
t x 1
0
1
0
t x 2
:
1
t x 15
Once the watchdog timer enabled setting WTE bit, it
cannot be disabled anymore, except by a system reset.
The watchdog timer is frozen during idle or power down
mode.
HWDR is a write only register. Its value after reset is 00h
which disables the watchdog operation.
HWDR is using TSC8051C1 Special Function Register
address, E6h.
Timer (4–bit)
Prescaler
(17–bit)
Load
Clear
Underflow
WTE
Internal
reset
Set
Internal bus
Write HWDR
fosc/12
Q
Figure 9. Watchdog timer block diagram
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| TSC8051C1XXX-12CGR | 8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-12IDD | 8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-12IDR | 8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-16CAR | 8-Bit Microcontroller for Digital Computer Monitors |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSC8051C1XXX-12CGR | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-12CHB | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-12CHD | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-12CHR | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-12CIB | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:8-Bit Microcontroller for Digital Computer Monitors |
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