参数资料
型号: TSC80C31-25IDD
厂商: ATMEL CORP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 25 MHz, MICROCONTROLLER, PQFP44
封装: PLASTIC, QFP-44
文件页数: 3/132页
文件大小: 10886K
代理商: TSC80C31-25IDD
11
7593L–AVR–09/12
AT90USB64/128
5.
AVR CPU core
5.1
Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
5.2
Architectural overview
Figure 5-1.
Block diagram of the AVR architecture.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Re-programmable Flash memory.
Flash
program
memory
Instruction
register
Instruction
decoder
Program
counter
Control lines
32 x 8
general
purpose
registrers
ALU
Status
and control
I/O lines
EEPROM
Data bus 8-bit
Data
SRAM
Direct
addressing
Indirect
addressing
Interrupt
unit
SPI
unit
Watchdog
timer
Analog
comparator
I/O Module 2
I/O Module1
I/O Module n
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