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参数资料
| 型号： | TSI206 |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 8/28页 |
| 文件大小： | 286K |
| 代理商： | TSI206 |
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Tsi206 Primary Side Monitor with Inrush Control
Datasheet
- 16 -
Tundra Semiconductor Corporation
80C7000_MA001_01 April 2006
PI-Link isolated interface to secondary
The PI-Link interface is designed to transmit power
system status information from the primary side to
the secondary side, while maintaining the required
isolation. Data transmission through the PI-Link is
unidirectional, from primary to secondary. The
PI-Link network is driven by the TX_H and TX_L
pins of the primary side device (for example, the
Tsi206), and connects into the RX input pin of the
secondary side device (for example, the Tsi257).
In Figure 1 on page 1, the isolated interface
connection is shown as a transformer. A few
additional components are necessary to block DC
and balance the transformer signals for noise
immunity, as shown in Figure 7 on page 17.
Note: The components must be physically located
within the dimensions shown in Figure 7 to
guarantee proper operation.
The required component values for the isolation
network are shown in Table 7. Capacitors C8 and
C9 provide safety isolation to fully meet the
requirements of IEC60950 for basic insulation.
R24acts as a high frequency filter in conjunction
with the pad input capacitance of the Tsi257, and
C10 provides DC blocking. Data is transmitted
across T1 as pulses of alternating polarity, and is
encoded using pulse position modulation.
The PI-Link isolated interface transmits the voltage
and current measurement values and the digital
status information to the secondary side device.
The transmitted information is as follows:
Voltage and current sample values
Input voltage (10-bit value)
Auxiliary voltage (8-bit or 10-bit value, refer to
Input current (8-bit value)
Voltage at FUSE_L and FUSE_H pins (8-bit
value)
Digital status bits
Any fault (this bit is set to one if any of the other
bits is set)
Fuse fail (high side or low side fuse open)
Brownout
Input overcurrent (OC)
Input overvoltage (OV)
SEAT pin status
Inrush complete
Input undervoltage (UV)
Any of the first four bits can be mapped to a GPIO
pin in the Tsi257 secondary side device. Refer to
the Tsi257 Power Subsystem Controller Software
Reference Manual
for detailed information on
configuring the Tsi257 GPIO pins.
Table 6 — Glitch filters - summary
Signal
Brick enable
Brick disable
Comment
BUSOFF
Masked for 800 ms after brick
is enabled
24 ms debounce before brick
is disabled
Initial mask to allow time for
secondary controller to start
SEAT
50 ms debounce for valid
SEAT to enable brick
10 ms debounce for invalid
SEAT to disable brick
FETA
800 ms debounce before
brick is enabled
800 ms debounce before
brick is disabled
UV
200 ms debounce before
brick is enabled
200
μs debounce before
brick is disabled
OV
200 ms debounce for both high and low transitions
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