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| 型号： | TSL1401CS-LF |
| 厂商： | AMS-TAOS USA Inc |
| 文件页数： | 5/19页 |
| 文件大小： | 680K |
| 描述： | IC OPTO SENSOR ARRAY CSP PCB MT |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TSL1401-CS-LFDKR |
TSL1401CSLF
128 ?1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E APRIL 2007
4
r
r
Copyright E 2007, TAOS Inc.
The LUMENOLOGY r Company
www.taosinc.com
Electrical Characteristics at f
clock
= 1 MHz, V
DD
= 5 V, T
A
= 25?/SPAN>C, ?/SPAN>
p
= 640 nm, t
int
= 5 ms,
R
L
= 330 ?/SPAN>, E
e
= 11 ?/SPAN>W/cm
2
(unless otherwise noted) (see Note 3 and Note 4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
out
Analog output voltage (white, average over 128 pixels)
See Note 4
1.6
2
2.4
V
V
drk
Analog output voltage (dark, average over 128 pixels)
E
e
= 0
0
0.1
0.2
V
PRNU
Pixel response nonuniformity
See Note 5
?%
?10%
Nonlinearity of analog output voltage
See Note 6
?.4%
FS
Output noise voltage
See Note 7
1
mVrms
R
e
Responsivity
See Note 8
25
35
44
V/
(糐/cm
2
)
V
DD
= 5 V, R
L
= 330 ?/DIV>
4.5
4.8
V
sat
Analog output saturation voltage
V
DD
= 3 V, R
L
= 330 ?/DIV>
2.5
2.8
V
V
DD
= 5 V, See Note 9
136
SE
Saturation exposure
V
DD
= 3 V, See Note 9
78
nJ/cm
2
DSNU
Dark signal nonuniformity
All pixels, E
e
= 0
See Note 10
0.02
0.05
V
IL
Image lag
See Note 11
0.5%
V
DD
= 5 V, E
e
= 0
2.8
4.5
I
DD
Supply current
V
DD
= 3 V, E
e
= 0
2.6
4.5
mA
I
IH
High-level input current
V
I
= V
DD
1
糀
I
IL
Low-level input current
V
I
= 0
1
糀
C
i
Input capacitance
5
pF
NOTES: 3. All measurements made with a 0.1 糉 capacitor connected between V
DD
and ground.
4. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
8. R
e(min)
= [V
out(min)
V
drk(max)
] ?/SPAN> (E
e
?/SPAN> t
int
)
9. SE(min) = [V
sat(min)
V
drk(min)
] ?/SPAN> )E
e
?/SPAN> t
int
) ?/SPAN> [V
out(max)
V
drk(min)
]
10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL +
V
out (IL)
* V
drk
V
out (white)
* V
drk
100
Timing Requirements (see Figure 1 and Figure 2)
MIN
NOM
MAX
UNIT
t
su(SI)
Setup time, serial input (see Note 12)
20
ns
t
h(SI)
Hold time, serial input (see Note 11 and Note 13)
0
ns
t
w
Pulse duration, clock high or low
50
ns
t
r
, t
f
Input transition (rise and fall) time
0
500
ns
t
qt
Pixel charge transfer time
20
約
NOTES: 12. Input pulses have the following characteristics: t
r
= 6 ns, t
f
= 6 ns.
13. SI must go low before the rising edge of the next clock pulse.
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