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参数资料
| 型号： | TSPC106AMGSU66CE |
| 厂商： | ATMEL CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, CBGA303 |
| 封装： | 21 X 25 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CICGA-303 |
| 文件页数： | 19/40页 |
| 文件大小： | 569K |
| 代理商： | TSPC106AMGSU66CE |
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26
TSPC106
2102B–HIREL–02/02
Input AC Specifications
Notes:
1. Input specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the 1.4V of the rising edge of
the input SYSCLK. Input and output timings are measured at the pin.
2. Processor and memory interface signals are specified from the rising edge of the 60x bus clock.
3. Group I input signals include the following processor, L2 and memory interface signals: A[0:31], PAR[0:7]/AR[1:8],BR[0:4],
BRL2,XATS,LBCLAIM,ADS,BA0,TV and HIT (when configured for external L2).
4. Group II input signals include the following processor and memory interface signals: TBST, TT[0:4], TSIZ[0:2], WT,CI,GBL,
AACK and TA.
5. Group III input signals include the following processor and memory interface signals: DL[0:31] and DH[0:31].
6. Group IV input signals include the following processor and L2 interface signals: TS,ARTRY,DIRTY_IN and HIT (when con-
figured for internal L2 controller).
7. PCI 3.3 V signaling environment signals are measured from 1.65V (VDD÷ 2) on the rising edge of SYSCLK to VOH =3.0Vor
VOL =0.3V.
PCI 5V signaling environment signals are measured from 1.65V (VDD÷ 2) on the rising edge of SYSCLK to VOH =2.4Vor VOL
= 0.55V.
8. Group V input signals include the following bussed PCI interface signals: FRAME,C/BE[0:3], AD[0:31], DEVSEL,IRDY,
TRDY,STOP,PAR,PERR, SERR,LOCK, FLSHREQ, and ISA_MASTER.
9. Group VI input signal is the point-to-point PCI GNT input signal.
10. The setup and hold time is with respect to the rising edge of HRST. Mode select inputs include the RCS0,FOE and DBG0
configuration inputs.
11. t
SYSCLK is the period of the external clock (SYSCLK) in nanoseconds (ns). When the unit is given as tSYSCLK the numbers
given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the
parameter in question.
12. These values are guaranteed by design and are not tested.
Table 17. Input AC Timing Specifications (V
DD = 3.3V± 5% dc, GND = 0Vdc, CL =50pF, -55°C ≤ TC ≤ 125°C)
Ref
Characteristic
66 MHz
83.3 MHz
Unit
Min
Max
Min
Max
10a
Group I input signals valid to SYSCLK (input
setup)
(1,2,3)
4.0
3.5
ns
10a
Group II input signals valid to SYSCLK (input
setup)
(1,2,4)
3.5
ns
10a
Group III input signals valid to SYSCLK (input
setup)
(1,2,5)
3.0
2.5
ns
10a
Group IV input signals valid to SYSCLK (input
setup)
(1,2,6)
5.0
4.0
ns
10b
Group V input signals valid to SYSCLK (input
setup)
(7, 8)
7.0
ns
10b
Group VI input signals valid to SYSCLK (input
setup)
(7, 9)
7.0
ns
11a
60x Bus Clock to group I - IV inputs invalid (input
hold)
(3,4,5,6)
00
ns
11b
SYSCLK to group V - VI inputs invalid (input hold)
(8,
9)
-0.5
ns
HRST pulsewidth
255x tSYSCLK
+100 s
255 x tSYSCLK
+100 s
10c
Mode select inputs valid to HRST (input setup)
(10,
11, 12)
3x t
SYSCLK
3xt
SYSCLK
ns
11c
HRST to mode select input invalid (input hold)
(10, 12)
1.0
ns
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相关代理商/技术参数 |
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|---|---|
| TSPC106AVG | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PCI Bus Bridge Memory Controller 66-83 MHz |
| TSPC106AVG66CE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
| TSPC106AVG66CG | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
| TSPC106AVG83CE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
| TSPC106AVG83CG | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
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