- 您现在的位置：买卖IC网 > PDF目录297617 > TSPC603PVG6ME 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 PDF资料下载
参数资料
| 型号： | TSPC603PVG6ME |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | CBGA-255 |
| 文件页数： | 20/38页 |
| 文件大小： | 704K |
| 代理商： | TSPC603PVG6ME |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页当前第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
TSPC603p
27/38
5.2. Instruction set and addressing modes
The following subsections describe the PowerPC instruction set and addressing modes in general.
5.2.1. PowerPC instruction set and addressing modes
All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent among all instruction
types, permitting efficient decoding to occur in parallel with operand accesses. This fixed instruction length and consistent format
greatly simplifies instruction pipelining.
5.2.1.1. PowerPC instruction set
The PowerPC instructions are divided into the following categories :
D Integer instructions - These include computational and logical instructions.
- Integer arithmetic instructions.
- Integer compare instructions.
- Integer logical instructions.
- Integer rotate and shift instructions.
D Floating-point instructions -These include floating-point computational instructions, as well as instructions that affect the
FPSCR.
- Floating-point arithmetic instructions.
- Floating-point multiply/add instructions.
- Floating-point rounding and conversion instructions.
- Floating-point compare instructions.
- Floating-point status and control instructions.
D Load/store instructions - These include integer and floating-point load and store instructions.
- Integer load and store instruction.
- Integer load and store multiple instructions.
- Floating-point load and store.
- Primitives used to construct atomic memory operations (lwarx and stwcx. instructions).
D Flow control instructions - These include branching instructions, condition register logical instructions, trap instructions, and
other instructions that affect the instruction flow.
- Branch and trap instructions.
- Condition register logical instructions.
D Processor control instructions - These instructions are used for synchronizing memory accesses and management of caches,
TLBs, and the segment registers.
- Move to/from SPR instructions.
- Move to/from MSR.
- Synchronize.
- Instruction synchronize.
D Memory control instruction - These instructions provide control of caches, TLBs, and segment registers.
- Supervisor-level cache management instructions.
- User-level cache instructions.
- Segment register manipulation instructions.
- Translation lookaside buffer management instructions.
Note that this grouping of the instructions does not indicate which execution unit executes a particular instruction or group of instruc-
tions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on single-precision (one
word) and double-precision (one double word) floating-point operands. The PowerPC architecture uses instructions that are four
bytes long and word-aligned. It provides for byte, half-word, and word operand loads and stores between memory and a set of 32
GPRs. It also provides for word and double-word operand loads and stores between memory and a set of 32 floating-point registers
(FPRs).
Computational instructions do not modify memory. To use a memory operand in a computation and then modify the same or another
memory location, the memory contents must be loaded into a register, modified, and then written back to the target location with
distinct instructions.
PowerPC processors follow the program flow when they are in the normal execution state. However, the flow of instructions can be
interrupted directly by the execution of an instruction or by an asynchronous event. Either kind of exception may cause one of several
components of the system software to be invoked.
5.2.1.2. Calculating effective addresses
The effective address (EA) is the 32-bit address computed by the processor when executing a memory access or branch instruction
or when fetching the next sequential instruction.
相关PDF资料 |
PDF描述 |
|---|---|
| TSPC603PMGB/C8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| TSPC603PMGB/C6ME | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
| TSPC603PMGB/C6LE | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
| TS(X)PC603PVGU/T8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| TS(X)PC603PMGB/C6LE | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSPC603R | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
发布紧急采购，3分钟左右您将得到回复。