- 您现在的位置：买卖IC网 > PDF目录297617 > TSPC603PVG6ME 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 PDF资料下载
参数资料
| 型号： | TSPC603PVG6ME |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | CBGA-255 |
| 文件页数： | 7/38页 |
| 文件大小： | 704K |
| 代理商： | TSPC603PVG6ME |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
TSPC603p
15/38
3.5.3.3. Doze Mode
Doze ode disables most functional units but maintains cache coherency by enabling the bus interface unit and snooping. A snoop hit
will cause the 603p to enable the data cache, copy the data back to memory, disable the cache, and fully return to the doze state.
D Most functional units disabled.
D Bus snooping and time base/decrementer still enabled.
D Dose mode sequence :
- Set doze bit (HID0[8) = 1).
- 603p enters doze mode after several processor clocks.
D Several methods of returning to full-power mode :
- Assert INT, SMI, MCP or decrementer interrupts.
- Assert hard reset or soft reset.
D Transition to full-power state takes no more than a few processor cycles.
D PLL running and locked to SYSCLK.
3.5.3.4. Nap Mode
The nap mode disables the 603p but still maintains the phase locked loop (PLL) and the time base/decrementer. The time base can
be used to restore the 603p to full-on state after a programmed amount of time. Because bus snooping is disabled for nap and sleep
mode, a hardware handshake using the quiesce request (QREQ) and quiesce acknowledge (QACK) signals are requires to maintain
data coherency. The 603p will assert the QREQ signal to indicate that it is ready to disable bus snooping. When the system has
ensured that snooping is no longer necessary, it will assert QACK and the 603p will enter the sleep or nap mode.
D Time base/decrementer still enabled.
D Most functional units disabled (including bus snooping).
D All nonessential input receivers disables.
D Nap mode sequence :
- Set nap bit (HID0[9] = 1).
- 603p asserts quiesce request (QREQ) signal.
- System asserts quiesce acknowledge (QACK) signal.
- 603p enters sleep mode after several processor clocks.
D Several methods of returning to full-power mode :
- Assert INT, SPI, MCP or decrementer interrupts.
- Assert hard reset or soft reset.
D Transition to full-power takes no more than a few processor cycles.
D PLL running and locked to SYSCLK.
3.5.3.5. Sleep Mode
Sleep mode consumes the least amount of power of the four modes since all functional units are disabled. To conserve the maximum
amount of power, the PLL may be disabled and the SYSCLK may be removed. Due to the fully static design of the 603p, internal
processor state is preserved when no internal clock is present. Because the time base and decrementer are disabled while the 603p
is in sleep mode, the 603p’s time base contents will have to be updated from an external time base following sleep mode if accurate
time-of-day maintenance is required. Before the 603p enters the sleep mode, the 603p will assert the QREQ signal to indicate that it is
ready to disable bus snooping. When the system has ensured that snooping is no longer necessary, it will assert QACK and the 603p
will enter the sleep mode.
D All functional units disabled (including bus snooping and time base).
D All nonessential input receivers disabled :
- Internal clock regenerators disabled.
- PLL still running (see below).
D Sleep mode sequence :
- Set sleep bit (HID0[10] = 1).
- 603p asserts quiesce request (QREQ).
- System asserts quiesce acknowledge (QACK).
- 603p enters sleep mode after several processor clocks.
D Several methods of returning to full-power mode :
- Assert INT, SMI, or MCP interrupts.
- Assert hard reset or soft reset.
D PLL may be disabled and SYSCLK may be removed while in sleep mode.
D Return to full-power mode after PLL and SYSCLK disabled in sleep mode :
- Enable SYSCLK.
- Reconfigure PLL into desired processor clock mode.
- System logic waits for PLL startup and relock time (100
msec).
- System logic asserts one of the sleep recovery signals (for example, INT or SMI).
相关PDF资料 |
PDF描述 |
|---|---|
| TSPC603PMGB/C8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| TSPC603PMGB/C6ME | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
| TSPC603PMGB/C6LE | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
| TS(X)PC603PVGU/T8ME | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| TS(X)PC603PMGB/C6LE | 32-BIT, 166 MHz, RISC PROCESSOR, CBGA255 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSPC603R | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RCAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8L | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
| TSPC603RMAB/Q8LC | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:PowerPC 603e RISC Microprocessor Family PID7t-603e |
发布紧急采购，3分钟左右您将得到回复。