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参数资料
| 型号： | TSPC603RVGSB/Q14LC |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | 21 X 21 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CERAMIC, CI-CGA-255 |
| 文件页数： | 132/132页 |
| 文件大小： | 10886K |
| 代理商： | TSPC603RVGSB/Q14LC |
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9
7593L–AVR–09/12
AT90USB64/128
2.2.8
Port E (PE7..PE0)
Port E is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the AT90USB64/128 as listed on
2.2.9
Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bidirectional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.2.10
D-
USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D-
connector pin with a serial 22
Ω resistor.
2.2.11
D+
USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+
connector pin with a serial 22
Ω resistor.
2.2.12
UGND
USB Pads Ground.
2.2.13
UVCC
USB Pads Internal Regulator Input supply voltage.
2.2.14
UCAP
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-
itor (1F).
2.2.15
VBUS
USB VBUS monitor and OTG negociations.
2.2.16
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page
58. Shorter pulses are not guaranteed to generate a reset.
2.2.17
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
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