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| 型号： | TSPC603RVGSB/Q14LC |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | 21 X 21 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CERAMIC, CI-CGA-255 |
| 文件页数： | 29/132页 |
| 文件大小： | 10886K |
| 代理商： | TSPC603RVGSB/Q14LC |
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198
ATmega8535(L)
2502K–AVR–10/06
Slave Transmitter Mode
In the Slave Transmitter mode, a number of data bytes are transmitted to a Master
Receiver (see Figure 92). All the status codes mentioned in this section assume that the
prescaler bits are zero or are masked to zero.
Figure 92. Data Transfer in Slave Transmitter Mode
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
The upper seven bits are the address to which the Two-wire Serial Interface will respond
when addressed by a Master. If the LSB is set, the TWI will respond to the general call
address (0x00), otherwise it will ignore the general call address.
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one
to enable the acknowledgement of the device’s own slave address or the general call
address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its
own slave address (or the general call address if enabled) followed by the data direction
bit. If the direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode
is entered. After its own slave address and the write bit have been received, the TWINT
Flag is set and a valid status code can be read from TWSR. The status code is used to
determine the appropriate software action. The appropriate action to be taken for each
status code is detailed in Table 78. The Slave Transmitter mode may also be entered if
arbitration is lost while the TWI is in the Master mode (see state 0xB0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of
the transfer. State 0xC0 or state 0xC8 will be entered, depending on whether the Master
Receiver transmits a NACK or ACK after the final byte. The TWI is switched to the not
addressed Slave mode, and will ignore the Master if it continues the transfer. Thus the
Master Receiver receives all “1” as serial data. State 0xC8 is entered if the Master
demands additional data bytes (by transmitting ACK), even though the Slave has trans-
mitted the last byte (TWEA zero and expecting NACK from the Master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the
Two-wire Serial Bus is still monitored and address recognition may resume at any time
TWAR
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
Value
Device’s Own Slave Address
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
Value
0
100
01
0
X
Device 3
Device n
SDA
SCL
........
R1
R2
V
CC
Device 2
MASTER
RECEIVER
Device 1
SLAVE
TRANSMITTER
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相关代理商/技术参数 |
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| TSPC603RVGSU/T14LC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
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