2–7
Input Signal
Output Signal
VO
VI
Coring Threshold
t
Figure 2–9. Transfer Curve of Coring Circuit
2.2.3
Chrominance Processing
A quadrature demodulator removes the U and V components from the composite signal in composite video
mode, or the U and V components from the chroma signal in S-video mode. The U/V signals then pass
through the gain control stage for chroma saturation adjustment. The U and V components pass through
a comb filter to eliminate cross-chrominance noise. Phase shifting the digitally-controlled oscillator controls
hue. The block includes an automatic color killer (ACK) circuit that suppresses the chroma processing when
the color burst of the video signal is weak or not present.
2.2.4
Clock Circuits
An Internal line-locked PLL generates the system and pixel clocks. Figure 2–10 shows a simplified clock
circuit diagram. The digital control oscillator generates the reference signal for the horizontal PLL.
The DCO outputs a signal that is fed to the D/A converter. The D/A converter outputs a line-locked clock
signal (LCLK). The DCO requires a 26.8 or a 24.576 MHz clock as an input. The input for the DCO may enter
terminal XTAL1 as TTL. Another input for the DCO may be a 26.8 or 24.576 MHz crystal connected across
terminals XTAL1 and XTAL2. The crystal input requires passive tuning circuits to activate the internal crystal
oscillator circuitry. Figure 2–11 shows the various reference clock configurations.
Lowpass Filter
Sync Detector
Phase
Detector
Loop
Filter
Line-Locked
Clock
PLL
Digital
Control
Oscillator
Crystal
Clock
Generator
DAC
Clock
Generator
Circuit
SCLK
PCLK
XTL1
XTL2
Digitized
Video
Figure 2–10. Clock Circuit Diagram