参数资料
型号: TVP5150PBSR
厂商: TEXAS INSTRUMENTS INC
元件分类: 颜色信号转换
英文描述: COLOR SIGNAL DECODER, PQFP32
封装: GREEN, PLASTIC, TQFP-32
文件页数: 4/68页
文件大小: 917K
代理商: TVP5150PBSR
Introduction
6
May 2006
SLES043A
Table 21. Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
I/O
DESCRIPTION
Digital Section
AVID
26
O
Active video indicator. This signal is high during the horizontal active time of the video output on the Y
and UV terminals. AVID continues to toggle during vertical blanking intervals. This terminal can be
placed in a high-impedance state.
DGND
19
I
Digital ground
DVDD
20
I
Digital supply. Connect to 1.8-V digital supply
FID/GLCO
23
O
FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd
field.
GLCO: This serial output carries color PLL information. A slave device can decode the information to
allow chroma frequency control from the TVP5150 device. Data is transmitted at the SCLK rate in
Genlock mode. In RTC mode, SCLK/4 is used.
HSYNC
25
O
Horizontal synchronization signal
INTREQ/GPCL/
VBLK
27
I/O
INTREQ: Interrupt request output.
GPCL: General-purpose control logic. This terminal has three functions:
1. General-purpose output. In this mode the state of GPCL is directly programmed via I2C.
2. Vertical blank output. In this mode the GPCL terminal is used to indicate the vertical blanking interval
of the output video. The beginning and end times of this signal are programmable via I2C.
3. Sync lock control input. In this mode when GPCL is high, the output clock frequencies and the sync
timing are forced to nominal values.
IO_DVDD
10
I
Digital supply. Connect to 3.3 V.
PDN
28
I
Power-down terminal (active low). Puts the device in standby mode. Preserves the value of the
registers.
RESETB
8
I
Active-low reset. RESETB can be used only when PDN = 1.
When RESETB is pulled low, it resets all the registers, restarts the internal microprocessor.
SCL
21
I/O
I2C serial clock (pullup to IO_DVDD with 1.2-k
resistor)
SCLK
9
O
System clock at either 1x or 2x the frequency of the pixel clock.
SDA
22
I/O
I2C serial data (pullup to IO_DVDD with 1.2-k
resistor)
VSYNC/PALI
24
O
VSYNC: Vertical synchronization signal
PALI: PAL line indicator or horizontal lock indicator
For the PAL line indicator, a 1 indicates a noninverted line, and a 0 indicates an inverted line.
XTAL1
XTAL2
5
6
I
O
External clock reference. The user may connect XTAL1 to an oscillator or to one terminal of a crystal
oscillator. The user may connect XTAL2 to the other terminal of the crystal oscillator or not connect
XTAL2 at all. One single 14.318-MHz crystal or oscillator is needed for ITUR BT.601 sampling, for all
supported standards.
YOUT[6:0]
12, 13,
14, 15,
16, 17, 18
I/O
Output decoded ITUR BT.656 output/YUV 422 output with discrete sync.
YOUT(7)/I2CSEL
11
I/O
I2CSEL: Determines address for I2C (sampled at startup). A pullup or pulldown register is needed
(>1 k
) to program the terminal to the desired address.
Logic 1: Address = 0xBA, Logic 0: Address = 0xB8
YOUT7: MSB of output decoded ITUR BT.656 output/YUV 422 output.
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