参数资料
型号: TVP5158PNPR
厂商: TEXAS INSTRUMENTS INC
元件分类: 颜色信号转换
英文描述: COLOR SIGNAL DECODER, PQFP128
封装: GREEN, PLASTIC, HTQFP-128
文件页数: 26/108页
文件大小: 1395K
代理商: TVP5158PNPR
FF
00
Y0
Y1
Y2
Y3
CLK_P
(27MHz)
CH1_D
00
XY
CH2_D
DVO_A_
[7:0]
Cb0
C r0
Cb2
Cr2
Cb 20
Y20
C r20
Y21
Cb 22
Y22
C r22
Y23
C b 24
Y24
Cr24
Y25
FF
00
Y0
Y1
Y2
Y3
00
XY
Cb0
C r0
Cb2
Cr2
Cb 20
Y20
C r20
Y21
Cb 22
Y22
C r22
Y23
C b 24
Y24
Cr24
Y25
CLK_N
(27MHz)
FF
00
Y0
CLK (108MHz)
CH1_D
00
XY
CH2_D
C b0
Cr50
Cb52
Cr52
C b20
Y 20
Cr20
Y21
Cb22
Y22
Cr92
Y93
Cb94
Y94
C r94
Y95
Y51
Y52
Y53
FF
00
Y0
00
XY
C b0
C b20
Y 20
Cr20
Y21
Cb22
Y22
Cr50
Cb52
Cr52
Y51
Y52
Y53
Cr92
Y93
Cb94
Y94
C r94
Y95
CH3_D
CH4_D
DVO_A_
[7:0]
SLES243E
– JULY 2009 – REVISED MARCH 2011
Table 3-6. Output Ports Configuration for Pixel-Interleaved Mode
Video Output
Cascade
I2C Address:
OCLK
Port A
Port B
Port C
Port D
Format
Stage
B0h
(MHz)
2-Ch D1
n/a
50h
54
Any 2 of 4 Ch
Hi-Z
4-Ch D1
n/a
60h
108
All 4 Ch
Hi-Z
4-Ch Half-D1
n/a
62h
54
All 4 Ch
Hi-Z
4-Ch CIF
n/a
63h
54
All 4 Ch
Hi-Z
3.8.2.1
2-Ch Pixel-Interleaved Mode
In 2-Ch pixel-interleaved mode, the video output data with D1 resolution from two video channels is
multiplexed pixel by pixel at 54 MHz. The output ports DVO_A and DVO_B are used in this mode. The
output clocks OCLK_P and OCLK_N are synchronized with each channel so that the backend chip can
de-multiplexed each video channel data easily. The video output from each channel is compatible with
ITU-R BT.656 format. Figure 3-10 shows the timing diagram for 2-Ch pixel-interleaved mode.
Figure 3-10. 2-Ch Pixel-Interleaved Mode Timing Diagram
3.8.2.2
4-Ch Pixel-Interleaved Mode
In 4-Ch pixel-interleaved mode, the video output data with D1 resolution from four video channels is
multiplexed pixel by pixel at 108 MHz. The output DVO_A is used in this mode. The output clock OCLK_P
is synchronized with all four channels data. Each channel video data is compatible with ITU-R BT.656
format. Figure 3-11 shows the timing diagram for 4-Ch pixel-interleaved mode.
Figure 3-11. 4-Ch Pixel-Interleaved Mode Timing Diagram
24
Functional Description
Copyright
2009–2011, Texas Instruments Incorporated
Product Folder Link(s): TVP5158 TVP5157 TVP5156
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