参数资料
| 型号： | TWL1103GQER |
| 厂商： | Texas Instruments |
| 文件页数： | 20/30页 |
| 文件大小： | 0K |
| 描述： | VOICE BAND AUDIO PROC 80-BGA |
| 标准包装： | 1 |
| 系列： | VBAP™ |
| 类型： | 音频处理器 |
| 应用： | 移动电话 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-VFBGA |
| 供应商设备封装： | 80-BGA MICROSTAR JUNIOR（5x5） |
| 包装： | 标准包装 |
| 其它名称： | 296-11095-6 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页当前第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页
TWL1103
VOICE-BAND AUDIO PROCESSOR (VBAP
)
SLWS108A – JULY 2000 – JANUARY 2001
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 10. I2C Bus Conditions
CONDITION
STATUS
DESCRIPTION
A
Bus not busy
Both data and clock lines remain at high.
B
Start data transfer
A high to low transition of the SDA line while the clock (SCL) is high determines a start condition.
All commands must proceed from a start condition.
C
Stop data transfer
A low to high transition of the SDA line while the clock (SCL) is high determines a stop condition.
All operations must end with a stop condition.
D
Data valid
The state of the data line represents valid data when, after a start condition, the data line is stable
for the duration of the high period of the clock signal.
I2C bus protocols
The data on the line must be changed during the low period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
When addressed, the VBAP generates an acknowledge after the reception of each byte. The master device
(microprocessor) must generate an extra clock pulse that is associated with this acknowledge bit.
The VBAP must pull down the SDA line during the acknowledge clock pulse so that the SDA line is at stable
low state during the high period of the acknowledge related clock pulse. Setup and hold times must be taken
into account. During read operations, a master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave (VBAP) must leave
the data line high to enable the master to generate the stop condition.
clock frequencies and sample rates
A fixed PCMSYN rate of 8 kHz determines the sampling rate.
相关PDF资料 |
PDF描述 |
|---|---|
| TXB0102DCUTG4 | IC VOLT-LVL TRANSL BI-DIR 8-US8 |
| TXB0104DG4 | IC VOLT-LEVEL TRANSLATOR 14-SOIC |
| ULN2803ANE4 | IC DARL TRANS ARRAY HV 18-DIP |
| ULQ2003ADR2G | TRANS ARRAY DARL 16-SOIC |
| UPC1663GV-E1-A | IC VIDEO AMP DIFF 8-SSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TWL1103PBS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TWL1103PBSR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TWL1103TPBSQ1 | 功能描述:音频 DSP Auto Cat Voice-Band Audio Processor RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| TWL1103TPBSRQ1 | 功能描述:音频 DSP Auto Cat Voice-Band Audio Processor RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| TWL1103T-Q1 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Automotive Catalog Voice-Band Audio Processor (VBAP) |
发布紧急采购，3分钟左右您将得到回复。