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参数资料
| 型号： | UBA2033TS/N2,118 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 6/18页 |
| 文件大小： | 0K |
| 描述： | IC FULL BRIDGE DRIVER 28-SSOP |
| 标准包装： | 1 |
| 配置： | 半桥 |
| 输入类型： | 自振荡 |
| 电流 - 峰： | 130mA |
| 配置数： | 1 |
| 输出数： | 4 |
| 高端电压 - 最大（自引导启动）： | 550V |
| 电源电压： | 10.5 V ~ 13.5 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 844 (CN2011-ZH PDF) |
| 其它名称： | 568-3326-6 |
NXP Semiconductors
HF full bridge driver IC
’Dead time’ can be increased by adding a resistor (for
slowly turning on the full bridge power FETs) and a diode
(for quickly turning off the full bridge power FETs) in
parallel, both in series with the gate drivers (see Fig.3).
Divider function
If pin DD = SGND, then the divider function is
enabled/present. If the divider function is present there is
no direct relation between the position of the bridge output
and the status of pin EXTDR.
Start-up delay
Normally, the circuit starts oscillating as soon as pin V DD or
HV reaches the level of release power drive. At this
Product specification
UBA2033
moment the gate drive voltage is equal to the voltage on
pin V DD for the low side transistors and V DD ? 0.6 V for the
high side transistors. If this voltage is too low for sufficient
drive of the MOSFETs the release of the power drive can
be delayed via pin SU.
A simple RC filter (R between pins V DD and SU;
C between pins SU and SGND) can be used to make a
delay, or a control signal from a processor can be used.
Bridge disable
The bridge disable function can be used to switch off all the
MOSFETs as soon as the voltage on pin BD exceeds the
bridge disable voltage (1.29 V). The bridge disable
function overrules all the other states.
Table 1
Logic table; note 1
DEVICE
INPUTS
OUTPUTS
STATUS
Start-up state
Oscillation state
BD
HIGH
LOW
HIGH
LOW
LOW
SU
X
X
X
LOW
HIGH
DD
X
X
X
X
HIGH
EXTDR
X
X
X
X
HIGH
GHL
LOW
LOW
LOW
LOW
LOW
GHR
LOW
LOW
LOW
LOW
HIGH
GLL
LOW
HIGH
LOW
HIGH
HIGH
GLR
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
LOW-to-HIGH
HIGH
HIGH-to-LOW
LOW
HIGH
HIGH
LOW
Note
1. X = don’t care
a) BD, SU and DD logic levels are with respect to SGND
b) EXTDR logic levels are with respect to V ? LVS
c) GHL logic levels are with respect to SHL
d) GHR logic levels are with respect to SHR
e) GLL and GLR logic levels are with respect to PGND
f) If pin DD = LOW the bridge enters the state (oscillation state and pin BD = LOW and pin SU = HIGH) in the
pre-defined position pin GHL and pin GLR = HIGH and pin GLL and pin GHR = LOW.
2002 Oct 08
6
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