参数资料
型号: UCC28250PWR
厂商: Texas Instruments
文件页数: 2/53页
文件大小: 0K
描述: IC REG CTRLR PWM CM/VM 20-TSSOP
标准包装: 2,000
PWM 型: 电流/电压模式
输出数: 1
频率 - 最大: 1MHz
占空比: 100%
电源电压: 4.7 V ~ 17 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
包装: 带卷 (TR)

SLUSA29C – APRIL 2010 – REVISED JULY 2011
ORDERING INFORMATION
TEMPERATURE RANGE
T A = T J
-40 ° C to 125 ° C
PACKAGE
Plastic 20-pin QFN (RGP)
Plastic 20-pin TSSOP (PW)
TAPE AND REEL QTY
250
3000
250
3000
PART NUMBER
UCC28250RGPT
UCC28250RGPR
UCC28250PWT
UCC28250PWR
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (1) (2) (unless otherwise noted)
PARAMETER
VALUE
UNIT
VDD
(3)
Input supply voltage
OUTA, OUTB, SRA and SRB
COMP
Input voltages on SS and EN
Input voltages on RT, PS, SP, ILIM, OVP, HICC, VSENSE, EA+ and EA-
Input voltage on RAMP/CS
Output voltage on VREF
-0.3 to 20.0
-0.3 to VDD + 0.3
-0.3 to VREF + 0.3
-0.3 to 5.5
-0.3 to 3.6
-0.3 to 4.3
-0.3 to 3.6
V
HBM
CDM
ESD rating
3k
2k
Lead temperature (soldering 10 sec) PW package
300
° C
(1)
(2)
(3)
Stresses beyond those listed under “ absolute maximum ratings ” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “ recommended operating
conditions ” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
THERMAL INFORMATION
UCC28250
UCC28250
THERMAL METRIC
RGP
20 PINS
PW (1)
20 PINS
UNITS
θ JA
Junction-to-ambient thermal resistance (2)
126 with hot spot,
104 without hot spot
60.3 with hot spot,
39.3 without hot spot
θ JC(top)
θ JB
Junction-to-case(top) thermal resistance
(4)
Junction-to-board thermal resistance
(3)
31.5
55.8
° C/W
θ JC(bottom)
Junction-to-case(bottom) thermal resistance
(5)
0.8
(1)
(2)
(3)
(4)
(5)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953 .
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2
Product Folder Link(s): UCC28250
Copyright ? 2010 – 2011, Texas Instruments Incorporated
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