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| 型号： | UCC28250PWR |
| 厂商： | Texas Instruments |
| 文件页数： | 33/53页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR PWM CM/VM 20-TSSOP |
| 标准包装： | 2,000 |
| PWM 型： | 电流/电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 100% |
| 电源电压： | 4.7 V ~ 17 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 带卷 (TR) |
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SLUSA29C – APRIL 2010 – REVISED JULY 2011
Primary-Side Control
When the UCC28250 is sitting on the primary side, the internal error amplifier is connected as a voltage follower
and an extra error amplifier is needed on the secondary side for closed loop control. The error amplifier
VOUT
UCC28250
R Z3
C Z3
R O2
R Z2
+
C P1
C Z2
VSENSE
VREF
COMP
FB/EA-
R O1
REF/EA+
+
+
SS
External
Reference
C SS
Figure 41. Error Amplifier Setup for Primary-Side Control
In the above configuration, the UCC28250 can only see the control loop feedback voltage, and cannot directly
access the output voltage. The design of the soft-start time is critical to achieve optimal pre-biased start up
performance. Some trial and error approaches are needed to achieve optimal performance. It is also important to
choose the appropriate ramp amplitude. Refer to the ramp section discussion on the detailed design procedure
for choosing ramp generation components.
During soft start, regardless of the pre-biased condition, the output voltage is always lower than the regulation
voltage, so that the feedback loop is always saturated. When the internal error amplifier is connected as a
voltage follower, the COMP voltage follows the lower of the voltage on the RER/EA+ pin and the SS pin. Since
the feedback loop is saturated, the COMP pin always follows the SS pin voltage, until the output voltage
becomes regulated and the feedback voltage takes over. In this control method, the output voltage control loop is
always saturated, and the controller soft starts the COMP pin voltage. Therefore, it is called open loop soft start.
The primary-side switch duty cycle is controlled by the COMP pin voltage and by the RAMP/CS pin voltage.
During soft start, the COMP pin voltage follows the SS pin as it is rising, so the primary-side switch duty cycle
keeps increasing. When the output voltage becomes regulated, the feedback voltage becomes less than the SS
pin voltage and the primary-side switch comes controlled by the control loop.
For the primary-side control setup, because output voltage is not directly accessible, the internal pre-biased start
up loop is disabled by connecting VSENSE to VREF. Instead, the internal ramp used to generate the
synchronous rectifier duty cycle is fixed, with the peak voltage of 3 V. The duty cycle of the synchronous rectifier
increases as the SS pin voltage increases. When the SS pin voltage reaches 2.9 V, the soft start is considered
finished and the synchronous rectifier duty cycle becomes the complementary of the primary-side switch duty
cycle, minus the programmed dead time. Because of different COMP pin voltages at different line voltages, the
SR duty cycle generated by the internal ramp might be different than the complementary of the primary-side
switch duty cycle (1-D). If the duty cycle is too large, the internal logic is able to limit the duty cycle to (1-D).
However, if the duty cycle is too small, when the soft start is finished, the SR duty cycle has a sudden change,
which will cause output voltage disturbance. To optimize the pre-biased start up performance, it is recommended
that the duty cycle change at the end of soft start be as small as possible.
Copyright ? 2010 – 2011, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
33
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