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参数资料
| 型号： | UPD4990AC-A |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP14 |
| 封装： | DIP-14 |
| 文件页数： | 11/51页 |
| 文件大小： | 211K |
| 代理商： | UPD4990AC-A |
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14
CHAPTER 2 FUNCTION SPECIFICATION
(2) REGISTER SHIFT COMMAND (C3’, C2’, C1’, C0’ = 0, 0, 0, 1)
Data of 48 bit shift register and 4 bit command register is equal 52 bit shift register C0’ of command register
is connected input of 48 bit shift register. Data of DATA IN is read at positive edge of CLK and LSB of 48 bit
shift register (B0) appeares to DATA OUT.
(3) TIME SET & COUNTER HOLD COMMANDS (C3’, C2’, C1’, C0’ = 0, 0, 1, 0)
Data of 48 bit shift register is set up to time counter, and 10th stage to 15th stage of 15 stages divider are reset.
After command is read, shift register is held and time counter is stopping. Time counter begin to count up after
next command is read. And the error of setting up is
±15.625 ms. LSB of 48 bit shift register (B0) appeares
to DATA OUT.
48 bit Shift Register
Disable Shift
DATA OUT
Time Counter
Data of 48 bit shift register isn't shifted
Data of 48 bit shift register is
transferred to time counter.
15 stage divider
10
115
32 kHz
Time counter is stopping and 10th stage
to 15th stage of 15 stages divider are reset.
"0" level
DATA IN
D
Command
Register
D
CK
CLK
LSB of 48 bit
shift register
(B0) "1" or "0"
DATA IN
48 bit Shift Register
D
Shift
Time Counter
Time counter continue to count up.
Divider
32 kHz
1 Hz
DATA OUT
LSB of 48 bit shift
register. (B0)
"1" or "0"
Data of 52 bit shift register is shifted
at positive edge of CLK
Command
Register
D
CK
CLK
C3, C2, C1, C0,
B47, B46, B0
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