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参数资料
| 型号： | UPD4990AC-A |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP14 |
| 封装： | DIP-14 |
| 文件页数： | 9/51页 |
| 文件大小： | 211K |
| 代理商： | UPD4990AC-A |
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12
CHAPTER 2 FUNCTION SPECIFICATION
(3) TIME SET & COUNTER HOLD COMMAND (C2, C1, C0 = 0, 1, 0)
Data of 40 bit shift register is set up time counter and 10th stage to 15th stage of 15 stages divider are reset.
After command is read, data of 40 bit shift register doesn’t shift and time counter is stopping. Time counter
begin to count up when next command is read. The error of setting up is
±15.625 ms.* LSB of 40 bit shift
register (B0) appeares to DATA OUT.
40 bit Shift Register
CLK
CK
Disable Shift
DATA OUT
Time Counter
Data is not able to shift.
Data is set up time counter
15 stage divider
10
115
32 kHz
Time counter is stopping and reset
10th stage to 15th stage of 15 stages divider.
"0"
* In case of
PD1990A, the error of setting up is ±31.25 ms.
(4) TIME READ COMMAND (C2, C1, C0 = 0, 1, 1)
Data of time counter is transferred to 40 bit shift register. Data is fixed when next command is read. 40 bit
shift register is held, and 1 Hz* (Duty = 50 %) appeares to DATA OUT.
40 bit Shift Register
CLK
CK
Disable Shift
1 Hz
Time Counter
Data of 40 bit shift register isn't shifted.
Data of time counter is set up
to 40 bit shift register
Divider
32 kHz
Time counter continue to count up.
1 Hz
DATA OUT
* 0.5 Hz appeares in case of
PD1990A.
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