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参数资料
型号： UPD78F9511GR-JJG-A
厂商： Renesas Electronics America
文件页数： 5/175页
文件大小： 0K
描述： MCU 8BIT SGL CHIP 16PIN
标准包装： 400
系列： 78K0S/Kx1+
核心处理器： 78K0S
芯体尺寸： 8-位
速度： 10MHz
外围设备： LVD，POR，PWM，WDT
输入/输出数： 13
程序存储器容量： 2KB（2K x 8）
程序存储器类型： 闪存
RAM 容量： 128 x 8
电压 - 电源 (Vcc/Vdd)： 2 V ~ 5.5 V
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 16-SSOP（0.173"，4.40mm 宽）
包装： 托盘
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U16994EJ6V0UD
100
Cautions 3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.
<1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the
operation of 16-bit timer counter 00 (TM00) is enabled
→ If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
<2> If the TM00 operation is stopped while the TI0n0 pin is at high level, TM00 operation
is then enabled after a low level is input to the TI0n0 pin
→ If the falling edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is
enabled.
<3> If the TM00 operation is stopped while the TI0n0 pin is at low level, TM00 operation
is then enabled after a high level is input to the TI0n0 pin
→ If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
4. The sampling clock used to eliminate noise differs when the valid edge of TI000 is used
as the count clock and when it is used as a capture trigger. In the former case, the count
clock is fXP, and in the latter case the count clock is selected by prescaler mode register
00 (PRM00). The capture operation is not performed until the valid edge is sampled and
the valid level is detected twice, thus eliminating noise with a short pulse width.
5. When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a timer
output pin (TO00). When using P21 as the timer output pin (TO00), it cannot be used as
the input pin (TI010) of the valid edge.
Remark
n = 0, 1
(5) Port mode register 2 (PM2) and port mode control register 2 (PMC2)
Note
When using the P21/TO00/TI010/ANI1/INTP0 pin for timer output, clear PM21, the output latch of P21, and
PMC21 to 0.
When using the P20/TI000/TOH1/ANI0 and P21/TO00/TI010/ANI1/INTP0 pins as a timer input, set PM20 and
PM21 to 1, and clear PMC20 and PMC21 to 0.
At this time, the output latches of P20 and P21 can be either 0 or 1.
PM2 and PMC2 are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the value of PM2 to FFH, and clears the value of PMC2 to 00H.
Note
μPD78F921x only
Figure 6-9. Format of Port Mode Register 2 (PM2)
Address: FF22H After reset: FFH R/W
7
6
5
4
3
2
1
0
1
PM23
PM22
PM21
PM20
PM2n
P2n pin I/O mode selection (n = 0 to 3)
0
Output mode (output buffer on)
Symbol
PM2
1
Input mode (output buffer off)
<R>
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