参数资料
型号: UPD78F9511GR-JJG-A
厂商: Renesas Electronics America
文件页数: 75/175页
文件大小: 0K
描述: MCU 8BIT SGL CHIP 16PIN
标准包装: 400
系列: 78K0S/Kx1+
核心处理器: 78K0S
芯体尺寸: 8-位
速度: 10MHz
外围设备: LVD,POR,PWM,WDT
输入/输出数: 13
程序存储器容量: 2KB(2K x 8)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 16-SSOP(0.173",4.40mm 宽)
包装: 托盘
CHAPTER 9 A/D CONVERTER (
μPD78F921x ONLY)
User’s Manual U16994EJ6V0UD
164
(2) Analog input channel specification register (ADS)
This register specifies the input port of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-5. Format of Analog Input Channel Specification Register (ADS)
ADS0
ADS1
0
Analog input channel specification
ANI0
ANI1
ANI2
ANI3
ADS0
0
1
0
1
ADS1
0
1
0
1
2
3
4
5
6
7
ADS
Address: FF81H
After reset: 00H
R/W
Symbol
Caution
Be sure to clear bits 2 to 7 of ADS to 0.
(3) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The higher six bits are fixed to 0. Each
time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is
stored in ADCR in order starting from bit 1 of FF19H. FF19H indicates the higher 2 bits of the conversion result,
and FF18H indicates the lower 8 bits of the conversion result.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation makes ADCR undefined.
Figure 9-6. Format of 10-bit A/D Conversion Result Register (ADCR)
Symbol
Address: FF18H, FF19H
After reset: Undefined
R
FF19H
FF18H
0
ADCR
Caution
When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined.
Read the
conversion result following conversion completion before writing to ADM and ADS.
Using timing other than the above may cause an incorrect conversion result to be read.
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