参数资料
型号: UPSD3212AV-24T6T
厂商: 意法半导体
英文描述: Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
中文描述: 闪存可编程系统设备与8032具有USB和可编程逻辑控制器
文件页数: 88/163页
文件大小: 2844K
代理商: UPSD3212AV-24T6T
uPSD3212A, uPSD3212C, uPSD3212CV
88/163
PSD MODULE
The PSD Module provides configurable
Program and Data memories to the 8032 CPU
core (MCU). In addition, it has its own set of I/
O ports and a PLD with 16 macrocells for
general logic implementation.
Ports A,B,C, and D are general purpose
programmable I/O ports that have a port
architecture which is different from the I/O
ports in the MCU Module.
The PSD Module communicates with the MCU
Module through the internal address, data bus
(A0-A15, D0-D7) and control signals (RD, WR,
PSEN, ALE, RESET). The user defines the
Decoding PLD in the PSDsoft Development
Tool and can map the resources in the PSD
Module to any program or data address
space. Figure
46
shows the functional blocks
in the PSD Module.
Functional Overview
512Kbit Flash memory. This is the main Flash
memory. It is divided into 4 sectors (16KBytes
each) that can be accessed with user-
specified addresses.
Secondary 128Kbit Flash boot memory. It is
divided into 2 sectors (8KBytes each) that can
be accessed with user-specified addresses.
This secondary memory brings the ability to
execute code and update the main Flash
concurrently.
16Kbit SRAM. The SRAM’s contents can be
protected from a power failure by connecting
an external battery.
CPLD with 16 Output Micro Cells (OMCs) and
up to 20 Input Micro Cells (IMCs). The CPLD
may be used to efficiently implement a variety
of logic functions for internal and external
control. Examples include state machines,
loadable shift registers, and loadable
counters.
Decode PLD (DPLD) that decodes address for
selection of memory blocks in the PSD
Module.
Configurable I/O ports (Port A,B,C and D) that
can be used for the following functions:
MCU I/Os;
PLD I/Os;
Latched MCU address output; and
Special function I/Os.
Note:
I/O ports may be configured as open drain
outputs.
Built-in JTAG compliant serial port allows full-
chip, In-System Programmability (ISP). With
it, you can program a blank device or
reprogram a device in the factory or the field.
Internal page register that can be used to
expand the 8032 MCU Module address space
by a factor of 256.
Internal programmable Power Management
Unit (PMU) that supports a low-power mode
called Power-down Mode. The PMU can
automatically detect a lack of the 8032 CPU
core activity and put the PSD Module into
Power-down Mode.
Erase/WRITE cycles:
Flash memory - 100,000 minimum
PLD - 1,000 minimum
Data Retention: 15 year minimum (for Main
Flash memory, Boot, PLD and Configuration
bits)
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UPSD3212AV-24U6T Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
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相关代理商/技术参数
参数描述
UPSD3212AV-24U6T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
UPSD3212AV-40T6T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
UPSD3212AV-40U6T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
UPSD3212C 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
UPSD3212C-24T1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM