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参数资料
型号： uPSD3212CV
厂商： 意法半导体
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(带8032微控制器内核和16Kbit SRAM的FLASH可编程系统器件)
中文描述： 闪存可编程系统设备与8032微控制器内核和16Kbit的SRAM（带8032微控制器内核和16Kbit SRAM的的闪存可编程系统器件）
文件页数： 117/151页
文件大小： 1194K
代理商： UPSD3212CV
117/151
uPSD3212C, uPSD3212CV
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
The JTAG Serial Interface pins (TMS, TCK, TDI,
TDO) are dedicated pins on Port C (see Table 83).
All memory blocks (primary and secondary Flash
memory), PLD logic, and PSD MODULE Configu-
ration Register Bits may be programmed through
the JTAG Serial Interface block. A blank device
can be mounted on a printed circuit board and pro-
grammed using JTAG.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up Program and Erase cycles.
By default, on a blank device (as shipped from the
factory or after erasure), four pins on Port C are
the basic JTAG signals TMS, TCK, TDI, and TDO
.
Standard JTAG Signals
At power-up, the standard JTAG pins are inputs,
waiting for a JTAG serial command from an exter-
nal JTAG controller device (such as FlashLINK or
Automated Test Equipment). When the enabling
command is received, TDO becomes an output
and the JTAG channel is fully functional. The
same command that enables the JTAG channel
may optionally enable the two additional JTAG sig-
nals, TSTAT and TERR.
The RESET input to the uPS3200 should be active
during JTAG programming. The active RESET
puts the MCU module into RESET Mode while the
PSD Module is being programmed. See Applica-
tion Note AN1153 for more details on JTAG In-
System Programming (ISP).
The uPSD321X Devices supports JTAG In-Sys-
tem-Configuration (ISC) commands, but not
Boundary Scan. The PSDsoft Express software
tool and FlashLINK JTAG programming cable im-
plement the JTAG In-System-Configuration (ISC)
commands.
Table 83. JTAG Port Signals
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an “ISC_ENABLE” command received
over the four standard JTAG signals (TMS, TCK,
TDI, and TDO). They are used to speed Program
and Erase cycles by indicating status on uPDS
signals instead of having to scan the status out se-
rially using the standard JTAG channel. See Appli-
cation Note
AN1153
.
TERR indicates if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until an
“ISC_CLEAR” command is executed or a chip Re-
set (RESET) pulse is received after an
“ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy de-
scribed in the section entitled “Ready/Busy (PC3),”
page 83. TSTAT is High when the PSD MODULE
device is in READ Mode (primary and secondary
Flash memory contents can be read). TSTAT is
Low when Flash memory Program or Erase cycles
are in progress, and also when data is being writ-
ten to the secondary Flash memory.
TSTAT and TERR can be configured as “open
drain” type signals during an “ISC_ENABLE” com-
mand.
Security and Flash memory Protection
When the Security Bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured blank state. The Security Bit can be
set in PSDsoft Express Configuration.
All primary and secondary Flash memory sectors
can individually be sector protected against era-
sures. The sector protect bits can be set in PSD-
soft Express Configuration.
INITIAL DELIVERY STATE
When delivered from ST, the uPSD321X Devices
have all bits in the memory and PLDs set to '1.'
The code, configuration, and PLD logic are loaded
using the programming procedure. Information for
programming the device is available directly from
ST. Please contact your local sales representa-
tive.
Port C Pin
JTAG Signals
Description
PC0
TMS
Mode Select
PC1
TCK
Clock
PC3
TSTAT
Status (optional)
PC4
TERR
Error Flag (optional)
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
相关PDF资料
PDF描述
uPSD3212 Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可编程系统器件)
UPSD3215A-24T1 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
UPSD3215AV-40T6T 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
UPSD3215BV-24U1 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
UPSD3233A-40T6 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
相关代理商/技术参数
参数描述
UPSD3212CV-24T1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM
UPSD3212CV-24T6 功能描述:8位微控制器 -MCU 3.0V 512K 24MHz RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
UPSD3212CV-24T6T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
UPSD3212CV-24U1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM
UPSD3212CV-24U6 功能描述:8位微控制器 -MCU 3.0V 512K 24MHz RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
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