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参数资料
| 型号： | UPSD3213B-40T6T |
| 厂商： | 意法半导体 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| 中文描述： | 闪存可编程系统设备与8032微控制器核心和64Kbit SRAM的 |
| 文件页数： | 117/176页 |
| 文件大小： | 1081K |
| 代理商： | UPSD3213B-40T6T |
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μ
PSD323X
Example.
FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
ment 0. You can see that half of theprimary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example.
Note:
An equation that defined FS1 to anywhere
in the range of 8000h to BFFFh would notbe valid.
Figure 54 shows the priority levels for all memory
components. Anycomponent on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not overlap. Level one has the highest priority and
level 3 has the lowest.
Memory Select Configuration in Program and
Data Spaces.
The MCU Core has separate ad-
dress spaces for Program memory and Data
memory. Any of the memories within the PSD
MODULE can reside ineither space or both spac-
es. This is controlled through manipulation of the
VM Register that resides in the CSIOP space.
The VM Register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-the-fly.
For example, youmay wish to haveSRAM and pri-
mary Flash memory in the Data space atBoot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the primary and
secondary Flash memories. This is easily done
with the VM Register by using PSDsoft Express
Configuration to configure it for Boot-up and hav-
ing theMCU change it when desired. Table 89 de-
scribes the VM Register.
Figure 54. Priority Level of Memory and I/O
Components in the PSD MODULE
Table 89. VM Register
Level
1
SRAM, I/O,
or
PeripheralI/O
Level
2
Secondar
y
Non-VolatileMemory
Highest Priority
Level
3
Primary Flash Memory
Bit 7
PIO_EN
Bit 6
Bit 5
Bit 4
Primary
FL_Data
Bit 3
Secondary Data
Bit 2
Primary
FL_Code
Bit 1
Secondary Code
Bit 0
SRAM_Code
0 =disable
PIO Mode
not used
not used
0 = RD
can’t
access
Flash
memory
0 = RD can’t
access Secondary
Flash memory
0 = PSEN
can’t
access
Flash
memory
0 = PSEN can’t
access Secondary
Flash memory
0 = PSEN
can’t
access
SRAM
1= enable
PIO Mode
not used
not used
1 = RD
access
Flash
memory
1 = RD access
Secondary Flash
memory
1 = PSEN
access
Flash
memory
1 = PSEN access
Secondary Flash
memory
1 = PSEN
access
SRAM
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相关代理商/技术参数 |
参数描述 |
|---|---|
| UPSD3213B-40U1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3213B-40U1T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3213B-40U6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3213B-40U6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3213BV-24T1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
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