- 您现在的位置：买卖IC网 > PDF目录361590 > UPSD3213B-40T6T (意法半导体) Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM PDF资料下载
参数资料
| 型号： | UPSD3213B-40T6T |
| 厂商： | 意法半导体 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| 中文描述： | 闪存可编程系统设备与8032微控制器核心和64Kbit SRAM的 |
| 文件页数： | 27/176页 |
| 文件大小： | 1081K |
| 代理商： | UPSD3213B-40T6T |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页
27/176
μ
PSD323X
Boolean Instructions
The
μ
PSD323XDevices contain a complete Bool-
ean (single-bit) processor. One page of the inter-
nal RAM contains 128 address-able bits, and the
SFR spacecan supportup to 128addressable bits
as well. All of the port lines are bit-addressable,
and each one canbe treated as a separate single-
bit port.The instructionsthat access these bits are
not just conditional branches, but a complete
menu of move, set, clear, complement, OR and
AND instructions. These kinds of bit operations
are not easily obtained in other architectures with
any amount of byte-oriented software.
The instruction set for the Boolean processor is
shown in Table 12. All bits accesses are by direct
addressing.
Bit addresses 00h through 7Fh are in the Lower
128, and bit ad-dresses 80h through FFh are in
SFR space.
Note how easily an internal flag can be moved to
a port pin:
MOV C,FLAG
MOV P1.0,C
In this example, FLAG is the name of any addres-
sable bit in the Lower 128 or SFR space. An I/O
line (the LSB of Port 1, in this case) is set or
cleared depending on whether the Flag Bit is ’1’ or
’0.’
The Carry Bit in the PSW is used as the single-bit
Accumulator of the Boolean processor. Bit instruc-
tions that refer to the Carry Bit as C assemble as
Carry-specific instructions (CLR C, etc.). The Car-
ry Bit also has a direct address, since it resides in
the PSW register, which is bit-addressable.
Note:
The Boolean instruction set includes ANL
and ORL operations, but not the XRL (Exclusive
OR) operation. An XRL operation is simple to im-
plement in software. Suppose, for example,it isre-
quired to form the Exclusive OR of two bits:
C = bit 1 .XRL. bit2
The software to do that could be as follows:
MOV C , bit1
JNB bit2, OVER
CPL C
OVER: (continue)
First, Bit 1 is moved to the Carry. If bit2 = 0, then
C now contains the correct result. That is, Bit 1
.XRL. bit2 = bit1 if bit2 = 0. On the other hand, if
bit2 = 1, C now contains the complement of the
correct result. It need only be inverted (CPL C) to
complete the operation.
This codeuses theJNB instruction, one of a series
of bit-test instructions which execute a jump if the
addressed bit is set (JC, JB, JBC) or if the ad-
dressed bit is not set (JNC, JNB). In the above
case, Bit 2 is being tested, and if bit2 = 0, the CPL
C instruction is jumped over.
JBC executes the jump if the addressed bit is set,
and also clears the bit. Thus a flag can be tested
and cleared in one operation. All the PSW bits are
directly addressable, so the Parity Bit, or the gen-
eral-purpose flags, for example, are also available
to the bit-test instructions.
Table 12. Boolean Instructions
Relative Offset
The destination address for these jumps is speci-
fied to the assembler by a label or by an actual ad-
dress
in
Program
memory.
destination address assembles to a relative offset
byte. This is a signed (two’s complement) offset
bytewhich isadded to the PC in two’scomplement
arithmetic if the jump is executed.
The range of the jump is therefore -128 to +127
Program Memory bytesrelative to the first bytefol-
lowing the instruction.
How-ever,
the
Mnemonic
Operation
ANL C,bit
C = A .AND. bit
ANL C,/bit
C = C .AND. .NOT.bit
ORL C,bit
C = A .OR. bit
ORL C,/bit
C = C .OR. .NOT.bit
MOV C,bit
C = bit
MOV bit,C
bit = C
CLR C
C = 0
CLR bit
bit = 0
SETB C
C = 1
SETB bit
bit = 1
CPL C
C = .NOT.C
CPL bit
bit = .NOT.bit
JC rel
Jump if C =1
JNC rel
Jump if C = 0
JB bit,rel
Jump if bit =1
JNB bit,rel
Jump if bit = 0
JBC bit,rel
Jump if bit = 1; CLR bit
相关PDF资料 |
PDF描述 |
|---|---|
| UPSD3213B-40U1T | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3213BV-40U6T | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3214A-40U1T | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3214A-40U6T | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3214AV-24T1T | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| UPSD3213B-40U1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3213B-40U1T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3213B-40U6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3213B-40U6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3213BV-24T1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
发布紧急采购，3分钟左右您将得到回复。