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型号： UPSD3233AV-24T1T
厂商： 意法半导体
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
中文描述： 闪存可编程系统设备与8032微控制器核心和64Kbit SRAM的
文件页数： 120/176页
文件大小： 1081K
代理商： UPSD3233AV-24T1T
μ
PSD323X
120/176
PLDS
The PLDs bring programmable logic functionality
to the
μ
PSD. After specifying the logic for the
PLDs in PSDsoft Express, the logic is pro-
grammed intothe device and available upon Pow-
er-up.
Table 90. DPLD and CPLD Inputs
Note: 1. These inputs are not available in the 52-pin package.
The PSD MODULE contains two PLDs: the De-
code PLD (DPLD), and the Complex PLD (CPLD).
The PLDs are briefly discussed in the next few
paragraphs, and in more detail in the section enti-
tled “Decode PLD (DPLD),” page 122, and the
section entitled“Complex PLD(CPLD),” page123.
Figure 58 shows the configuration of the PLDs.
The DPLD performs address decoding for Select
signals for PSD MODULE components, such as
memory, registers, and I/O ports.
The CPLD can beused for logic functions, suchas
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the Out-
put Macrocells (OMC), Input Macrocells (IMC),
and the AND Array. The CPLD can also be used
to generate External Chip Select (ECS1-ECS2)
signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
The PLD input signals consist of internal MCU sig-
nals and external inputs from the I/O ports. The in-
put signals are shown in Table 90.
The Turbo Bit in PSD MODULE
The PLDs can minimize power consumption by
switching off when inputs remain unchanged for
an extended time of about 70ns. Resetting the
Turbo Bit to ’0’ (Bit 3 of PMMR0) automatically
places the PLDs into standby if no inputs are
changing. Turning the Turbo Mode off increases
propagation delays while reducing power con-
sumption. See the section entitled “POWER MAN-
AGEMENT,” page 136, on how to set the Turbo
Bit.
Additionally, five bits are available in PMMR2 to
block MCU control signals from entering thePLDs.
This reducespower consumptionand can be used
only when these MCU control signals are not used
in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Input Source
Input Name
Number
of
Signals
MCU Address Bus
A15-A0
16
MCU Control Signals
PSEN, RD, WR,
ALE
4
RESET
RST
1
Power-down
PDN
1
Port A Input
Macrocells
1
PA7-PA0
8
Port B Input
Macrocells
PB7-PB0
8
Port C Input
Macrocells
PC7-PC0
8
Port D Inputs
PD2-PD1
2
Page Register
PGR7-PGR0
8
Macrocell AB
Feedback
MCELLAB.FB7-
FB0
8
Macrocell BC
Feedback
MCELLBC.FB7-
FB0
8
Flash memory
Program Status Bit
Ready/Busy
1
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