- 您现在的位置：买卖IC网 > PDF目录361590 > UPSD3233AV-24T1T (意法半导体) Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM PDF资料下载
参数资料
| 型号： | UPSD3233AV-24T1T |
| 厂商： | 意法半导体 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| 中文描述： | 闪存可编程系统设备与8032微控制器核心和64Kbit SRAM的 |
| 文件页数： | 53/176页 |
| 文件大小： | 1081K |
| 代理商： | UPSD3233AV-24T1T |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页当前第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页
53/176
μ
PSD323X
TIMER/COUNTERS (TIMER0, TIMER1 AND TIMER2)
The
μ
PSD323X Devices has three 16-bit Timer/
Counter registers: Timer 0, Timer 1 and Timer2.
All of them can be configured to operate either as
timers or event counters and are compatible with
standard 8032 architecture.
In the “Timer” function, the registeris incremented
every machine cycle. Thus, one can think of it as
counting machine cycles. Since a machine cycle
consists of 6 CPU clock periods, the count rate is
1/6 of the CPU clock frequency.
In the “Counter”function, theregister is increment-
ed in response to a 1-to-0 transition at its corre-
sponding external input pin, T0 or T1. In this
function, the external input is sampled during
S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in thenext cy-
cle, thecount is incremented. The new count value
appears in the register during S2P1 of the cycle
following the one in which the transition was de-
tected. Since it takes 2 machine cycles (12 CPU
clock periods) to recognize a 1-to-0 transition, the
maximum count rate is 1/12 of the CPU clock fre-
quency. There are norestrictions onthe duty cycle
of the external input signal, but to ensure that a
given level is sampled at least once before it
changes, it should be held for at least one full cy-
cle. In addition to the “Timer” or “Counter” selec-
tion, Timer0 and Timer1 have four operating
modes from which to select.
Timer0 and Timer1
The “Timer” or “Counter” function is selected by
control bits C/ T in the Special Function Register
TMOD. These Timer/Counters have four operat-
ing modes, which are selected by bit-pairs (M1,
M0) in TMOD.Modes 0, 1, and 2 are the same for
Timers/ Counters. Mode 3 is different. The four op-
erating modes are de-scribed in the following text.
Table 36. Control Register (TCON)
Table 37. Description of the TCON Bits
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
Symbol
Function
7
TF1
Timer 1overflow flag. Set by hardware onTimer/Counter overflow. Cleared by hardware
when processor vectors to interrupt routine
6
TR1
Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on or off
5
TF0
Timer 0 overflow flag. Set by hardier on Timer/Counter overflow. Cleared by hardware
when processor vectors to interrupt routine
4
TR0
Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on or off
3
IE1
Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared
when interrupt processed
2
IT1
Interrupt 1 Typecontrol bit. Set/cleared by software to specify falling-edge/low-level
triggered external interrupt
1
IE0
Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared
when interrupt processed
0
IT0
Interrupt 0 Typecontrol bit. Set/cleared by software to specify falling-edge/low-level
triggered external interrupt
相关PDF资料 |
PDF描述 |
|---|---|
| UPSD3233AV-24T6T | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3233BV-40T1T | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3233BV-40U6T | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3234AV-40U6T | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3213B-24U1T | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| UPSD3233AV-24T6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3233AV-24T6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3233AV-24U1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3233AV-24U1T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3233AV-24U6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
发布紧急采购，3分钟左右您将得到回复。