参数资料
型号: V2DIP1-48
厂商: FTDI, Future Technology Devices International Ltd
文件页数: 11/25页
文件大小: 0K
描述: MOD VINCULUM-II DEV 1 PORT 48DIP
标准包装: 5
系列: Vinculum-II
主要目的: 接口,USB 2.0 主机/控制器
嵌入式: 是,ASIC
已用 IC / 零件: VNC2-48Q
主要属性: 单路 A 型连接器,UART / 并行 FIFO / SPI 接口
次要属性: 第二个 USB 端口可通过引脚使用,交通 LED
已供物品:
产品目录页面: 634 (CN2011-ZH PDF)
相关产品: 768-1052-ND - MOD VINCULUM-II DEBUGGR/PROGRAMR
其它名称: 768-1057
Document Reference No.: FT_000236
V2DIP1-48 VNC2-48 Development Module Datasheet Version 1.01
Clearance No.: FTDI# 153
`
3.5 UART Interface
When the data and control buses are configured in UART mode, the interface implements a standard
asynchronous serial UART port with flow control. The UART can support baud rates from 300baud to
3Mbaud. The UART interface is described more fully in a Vinculum-II datasheet please refer to:- FTDI
3.5.1
Signal Description – UART Interface
The UART signals can be programmed to a choice of I/O pin available. Table 3.4 explains the available
pins for each of the UART signals.
Available Pins
J1-6, J1-11, J2-5, J2-10
J1-2, J1-8, J1-12, J2-9
J1-3, J1-9, J2-12, J2-8
J1-10, J2-11, J2-6
J1-6, J1-11, J2-5, J2-10
Name
uart_txd
uart_rxd#
uart_rts#
uart_cts#
uart_dtr#
Type
Output
Input
Output
Input
Output
Description
Transmit asynchronous data output
Receive asynchronous data input
Request To Send Control Output
Clear To Send Control Input
Data Acknowledge (Data Terminal
Ready Control) Output
J1-2, J1-8, J1-12, J2-9
uart_dsr#
Input
Data Request (Data Set Ready
Control) Input
J1-3, J1-9, J2-12, J2-8
J1-10, J2-11, J2-6
uart_dcd#
uart_ri#
Input
Input
Data Carrier Detect Control Input
Ring Indicator Control Input.
uart_ri# low can be used to resume
the PC USB Host controller from
suspend.
J1-6, J1-11, J2-5, J2-10
uart_tx_active
Output
Enable Transmit Data for RS485
designs. uart_tx_active may be used
to signal that a transmit operation is
in progress.The uart_tx_active signal
will be set high one bit-time before
data is transmitted and return low
one bit time after the last bit of a
data frame has been transmitted
Table 3.4 - Data and Control Bus Signal Mode Options – UART Interface
Copyright ? 2010 Future Technology Devices International Limited
10
相关PDF资料
PDF描述
V2DIP1-64 MOD VINCULUM-II DEV 1 PORT 64DIP
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V2DIP2-48 MOD VINCULUM-II DEV 2 PORT 48DIP
V2DIP2-64 MOD VINCULUM-II DEV 2 PORT 64DIP
V2F118X500Y3DDP VARISTOR CAP FEEDTHRU 50V 0805
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