- 您现在的位置：买卖IC网 > PDF目录1252 > V2DIP1-48 (FTDI, Future Technology Devices International Ltd)MOD VINCULUM-II DEV 1 PORT 48DIP PDF资料下载
参数资料
| 型号： | V2DIP1-48 |
| 厂商： | FTDI, Future Technology Devices International Ltd |
| 文件页数： | 13/25页 |
| 文件大小： | 0K |
| 描述： | MOD VINCULUM-II DEV 1 PORT 48DIP |
| 标准包装： | 5 |
| 系列： | Vinculum-II |
| 主要目的： | 接口，USB 2.0 主机/控制器 |
| 嵌入式： | 是，ASIC |
| 已用 IC / 零件： | VNC2-48Q |
| 主要属性： | 单路 A 型连接器，UART / 并行 FIFO / SPI 接口 |
| 次要属性： | 第二个 USB 端口可通过引脚使用，交通 LED |
| 已供物品： | 板 |
| 产品目录页面： | 634 (CN2011-ZH PDF) |
| 相关产品： | 768-1052-ND - MOD VINCULUM-II DEBUGGR/PROGRAMR |
| 其它名称： | 768-1057 |
Document Reference No.: FT_000236
V2DIP1-48 VNC2-48 Development Module Datasheet Version 1.01
Clearance No.: FTDI# 153
`
Table 3.6 - Data and Control Bus Signal Mode Options – SPI Master
3.7 Parallel FIFO Interface-Asynchronous Mode
The Parallel FIFO Asynchronous mode is functionally the same as the Parallel FIFO Interface present in
VDIP1 has an eight bit parallel data bus, individual read and write strobes and two hardware flow control
signals.
3.7.1 Signal Description - Parallel FIFO Interface
shows the Parallel FIFO Interface signals and the pins that they can be mapped.
Available Pins
J1-6, J1-11, J2-5, J2-10
J1-2, J1-8, J1-12, J2-9
J1-3, J1-9, J2-12, J2-8
J1-10, J2-11, J2-6
J1-6, J1-11, J2-5, J2-10
J1-2, J1-8, J1-12, J2-9
J1-3, J1-9, J2-12, J2-8
J1-10, J2-11, J2-6
J1-6, J1-11, J2-5, J2-10
Name
fifo_data[0]
fifo_data[1]
fifo_data[2]
fifo_data[3]
fifo_data[4]
fifo_data[5]
fifo_data[6]
fifo_data[7]
fifo_rxf#
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Output
Description
FIFO data bus Bit 0
FIFO data bus Bit 1
FIFO data bus Bit 2
FIFO data bus Bit 3
FIFO data bus Bit 4
FIFO data bus Bit 5
FIFO data bus Bit 6
FIFO data bus Bit 7
When high, do not read data from
the FIFO. When low, there is data
available in the FIFO which can be
read bystrobing RD# low, then high.
J1-2, J1-8, J1-12, J2-9
When high, do not write data into the
J1-3, J1-9, J2-12, J2-8
fifo_txe#
Output
FIFO. When low, data can be written
into the FIFO by strobing WR high,
then low.
Enables the current FIFO data byte
on D0...D7 when low. Fetches the
J1-10, J2-11, J2-6
fifo_rd#
Input
next FIFO data byte (if available)
from the receive FIFO buffer when
RD# goes from high to low
Writes the data byte on the D0...D7
fifo_wr#
Input
pins into the transmit FIFO buffer
when WR goes from high to low.
Table 3.7 - Data and Control Bus Signal Mode Options – Parallel FIFO Interface
Copyright ? 2010 Future Technology Devices International Limited
12
相关PDF资料 |
PDF描述 |
|---|---|
| V2DIP1-64 | MOD VINCULUM-II DEV 1 PORT 64DIP |
| V2DIP2-32 | MOD VINCULUM-II DEV 2 PORT 32DIP |
| V2DIP2-48 | MOD VINCULUM-II DEV 2 PORT 48DIP |
| V2DIP2-64 | MOD VINCULUM-II DEV 2 PORT 64DIP |
| V2F118X500Y3DDP | VARISTOR CAP FEEDTHRU 50V 0805 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V2DIP1-64 | 功能描述:界面开发工具 USB Vinculum-II 64 Pin Mod 1 USB Port RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| V2DIP2-32 | 功能描述:界面开发工具 USB Vinculum-II 32 Pin Mod 2 USB Ports RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| V2DIP2-48 | 功能描述:界面开发工具 USB Vinculum-II 48 Pin Mod 2 USB Ports RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| V2DIP2-64 | 功能描述:界面开发工具 USB Vinculum-II 64 Pin Mod 2 USB Ports RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| V2E4-TA02 | 功能描述:电源管理IC开发工具 Random Vibe Module RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
发布紧急采购，3分钟左右您将得到回复。