参数资料
型号: V54C3256404VDUS7
厂商: PROMOS TECHNOLOGIES INC
元件分类: DRAM
英文描述: 64M X 4 SYNCHRONOUS DRAM, 5.4 ns, PBGA60
封装: MO-210, FBGA-60
文件页数: 55/56页
文件大小: 719K
代理商: V54C3256404VDUS7
ProMOS TECHNOLOGIES
V54C3256(16/80/40)4VD
8
V54C3256(16/80/40)4VD Rev1.9 August 2008
Capacitance*
TA = 0 to 70°C, VCC = (3.0~3.3) V ± 0.3 V, f = 1 Mhz
*Note:Capacitance is sampled and not 100% tested.
Absolute Maximum Ratings*
Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ..............................................1 W
Data out current (short circuit).......................50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Symbol
Parameter
Max. Unit
CI1
Input Capacitance (A0 to A12)
5
pF
CI2
Input Capacitance
RAS, CAS, WE, CS, CLK, CKE, DQM
5pF
CIO
Output Capacitance (I/O)
6.5
pF
CCLK
Input Capacitance (CLK)
4
pF
Block Diagram
Row decoder
Memory array
Bank 0
8192 x 512
x 16 bit
Co
lu
m
n
d
e
co
d
e
r
S
e
ns
e
am
pl
if
ie
r
&
I
(O)
bu
s
Row decoder
Memory array
Bank 1
8192 x 512
x16 bit
C
o
lu
mn
de
code
r
S
e
ns
e
am
pl
if
ie
r&
I
(O
)
b
u
s
Row decoder
Memory array
Bank 2
8192 x 512
x 16 bit
Co
lu
m
n
d
e
c
o
d
e
r
S
e
ns
e
am
pl
if
ie
r&
I
(O)
bu
s
Row decoder
Memory array
Bank 3
8192 x 512
x 16 bit
Co
lu
m
n
d
e
co
d
e
r
S
e
nse
am
pl
if
ie
r&
I(O
)b
u
s
Input buffer
Output buffer
I/O1-I/O16
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
A0 - A12, BA0, BA1
A0 - A8, AP, BA0, BA1
Control logic & timing generator
CLK
CK
E
CS
RA
S
CA
S
WE
LDQ
M
Row Addresses
Column Addresses
UDQM
x16 Configuration
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