- 您现在的位置：买卖IC网 > PDF目录202172 > V54C3256404VHUI6I (PROMOS TECHNOLOGIES INC) 64M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 PDF资料下载
参数资料
| 型号： | V54C3256404VHUI6I |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 INCH, GREEN, PLASTIC, TSOP2-54 |
| 文件页数： | 1/56页 |
| 文件大小： | 935K |
| 代理商： | V54C3256404VHUI6I |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页
1
V54C3256(16/80/40)4VH
256Mbit SDRAM
3.3 VOLT, TSOP II / FBGA PACKAGE
16M X 16, 32M X 8, 64M X 4
V54C3256(16/80/40)4VH Rev. 1.1 July 2010
67PC
7
System Frequency (fCK)
166 MHz
143 MHz
Clock Cycle Time (tCK3)
6 ns
7 ns
Clock Access Time (tAC3) CAS Latency = 3
5.4 ns
Clock Access Time (tAC2) CAS Latency = 2
5.4 ns
6 ns
Features
-
4 banks x 4Mbit x 16 organization
-
4 banks x 8Mbit x 8 organization
-
4 banks x16Mbit x 4 organization
-
High speed data transfer rates up to 166 MHz
-
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
-
Single Pulsed RAS Interface
-
Data Mask for Read/Write Control
-
Four Banks controlled by BA0 & BA1
-
Programmable CAS Latency: 2, 3
-
Programmable Wrap Sequence: Sequential or
Interleave
-
Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
-
Multiple Burst Read with Single Write Operation
-
Automatic and Controlled Precharge Command
-
Random Column Address every CLK (1-N Rule)
-
Power Down Mode
-
Auto Refresh and Self Refresh
-
Refresh Interval: 8192 cycles/64 ms
-
Available in 54 Pin TSOP II, 60 Ball FBGA, 54
Ball FBGA
-
LVTTL Interface
-
Single +3.3 V
±0.3 V Power Supply
Description
The V54C3256(16/80/40)4VH is a four bank Syn-
chronous DRAM organized as 4 banks x 4Mbit x 16,
4 banks x 8Mbit x 8, or 4 banks x 16Mbit x 4. The
V54C3256(16/80/40)4VH achieves high speed data
transfer rates up to 166 MHz by employing a chip
architecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T/S
6
7PC
7
Std.
L
U
0
°C to 70°C
Blank
-40
°C to 85°C
I
相关PDF资料 |
PDF描述 |
|---|---|
| V54C3256804VBS7 | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| V54C365164VCT8PC | 4M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| V55C2256164VBT10I | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| V55C3256164VGLK-10IPC | SYNCHRONOUS DRAM, PBGA54 |
| V55C3256164VGLK-7HPC | SYNCHRONOUS DRAM, PBGA54 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V54C3256404VS | 制造商:MOSEL 制造商全称:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| V54C3256404VT | 制造商:MOSEL 制造商全称:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| V54C3256804VAB | 制造商:MOSEL 制造商全称:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| V54C3256804VAT | 制造商:MOSEL 制造商全称:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| V54C3256804VB | 制造商:MOSEL 制造商全称:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
发布紧急采购，3分钟左右您将得到回复。