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参数资料
| 型号： | V55C3256164VGLK-7HPC |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PBGA54 |
| 封装： | GREEN, MO-210, FBGA-54 |
| 文件页数： | 1/55页 |
| 文件大小： | 711K |
| 代理商： | V55C3256164VGLK-7HPC |
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1
V55C3256164VG
256Mbit SDRAM
(3.0~3.3) VOLT, TSOP II / FBGA PACKAGE
16M X 16
V55C3256164VG Rev. 1.0 September 2008
PRELIMINARY
67PC
7
System Frequency (fCK)
166 MHz
143 MHz
Clock Cycle Time (tCK3)
6 ns
7 ns
Clock Access Time (tAC3) CAS Latency = 3
5.4 ns
Clock Access Time (tAC2) CAS Latency = 2
5.4 ns
6 ns
Features
■ 4 banks x 4Mbit x 16 organization
■ High speed data transfer rates up to 166 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Deep Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval:
8192 cycles/64ms [0 to 70o C (Commercial)];
8192 cycles/64ms [-40 to 85o C (Industrial)];
8192 cycles/32ms [-40 to 105o C (H)];
8192 cycles/32ms [-40 to 125o C (Extended)]
■ Available in 54 Pin TSOP II, 54 Ball FBGA
■ LVTTL Interface
■ Single (+3.0~3.3) V
±0.3 V Power Supply
■ Drive Strength (DS) Option: Full, 1/2, 1/4 and 1/8
■ Auto Temperature Compensated Self Refresh
(Auto TCSR)
■ Operating Temperature Range:
Commercial (0o to 70o C)
Industrial (-40o to +85o C)
H (-40o to +105o C)
Extended (-40o to +125o C)
The V55C3256164VG is a four bank Synchro-
nous DRAM organized as 4 banks x 4Mbit x 16. The
V55C3256164VG achieves high speed data trans-
fer rates up to 166 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at
higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 166
MHz is possible depending on burst length, CAS
latency and speed grade of the device.
Device Usage Chart
Operating Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T/C
6
7PC
7
Std.
L
U
0
°C to 70°C
Blank
-40o to 85o C
I
-40o to +105o C
H
-40o to +125o C
E
Description
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