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参数资料
| 型号： | V55C3256164VGLK-7HPC |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PBGA54 |
| 封装： | GREEN, MO-210, FBGA-54 |
| 文件页数： | 3/55页 |
| 文件大小： | 711K |
| 代理商： | V55C3256164VGLK-7HPC |
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V55C3256164VG Rev. 1.0 September 2008
ProMOS TECHNOLOGIES
V55C3256164VG
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to “high” at a
clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable
Latency tDQZ ). It also provides a data mask function for writes. When DQM is activated, the write operation
at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks must be pre-
charged and the necessary Precharge delay (trp) must occur before the SDRAM can enter the Power Down
mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK
and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device
can’t remain in Power Down mode longer than the Refresh period (tref) of the device. Exit from this mode is
performed by taking CKE “high”. One clock delay is required for mode entry and exit.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing ac-
cepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is
high when a Read Command is issued, the Read with Auto-Precharge function is initiated. The SDRAM
automatically enters the precharge operation one clock before the last data out for CAS latencies 2, two
clocks for CAS latencies 3 and three clocks for CAS latencies 4. If CA10 is high when a Write Command is
issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge
operation a time delay equal to tWR (Write recovery time) after the last data in.
Precharge Command
There is also a separate precharge command available. When RAS and WE are low and CAS is high at a
clock timing, it triggers the precharge
operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The
precharge command can be imposed one clock before the last data out for CAS latency = 2, two clocks before
the last data out for CAS latency = 3. Writes require a time delay twr from the last data out to apply the pre-
charge command.
Bank Selection by Address Bits:
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to terminate
the burst operation prematurely. These methods include using another Read or Write Command to interrupt
an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank,
or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future
Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read
or Write Command care must be taken to avoid I/O contention. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to use when terminating a burst operation before it has been
completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the
burst write cycle will be ignored. Data that is presented on the I/O pins before the Burst Stop Command is
registered will be written to the memory.
A10
BA0
BA1
0
Bank 0
0
1
Bank 1
0
1
0
Bank 2
0
1
Bank 3
1
X
all Banks
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